Tomas, I assume you mean buffer overruns, right? What type of CPU board are you using? I'm using a Geode and it is notoriously bad in terms of non-maskable System Management Interrupts which cause overflows. I had to lower the speed of transmission down to 57600 to avoid the overruns.
Take care, Josh -----Original Message----- From: [EMAIL PROTECTED] on behalf of Jan Kiszka Sent: Mon 5/5/2008 6:21 PM To: Tomas Kalibera Cc: [email protected] Subject: Re: [Xenomai-help] Loosing serial interrupt Tomas Kalibera wrote: > Hi, > > I am having problems with lost serial interrupts. Could you please > explain to me why this happens ? I am probably missing something > regarding scheduling in Xenomai... > I prepared a program that triggers the problem, at least on my system. > > Thanks, > > Tomas > > The program works on my system as follows: > > 1. I run the program, it prints > > In interrupt, LStatus: 96 > In interrupt, read char, LStatus: 96 > > [which means that it received a serial interrupt, because the > transmitter receiver is empty] > > 2. I send a single character to the program over serial line > > 3. the program wakes up (10 seconds after (1)) > > 4. the program prints > > I-NFO irq=4 hits=1 > PIC-ISR:0 PIC-IRR:0 PIC-IMR:128 UART-IIR:4 UART-LSR:97 UART-MSR:176 > > [which means the interrupt at Xenomai level hit only once, although it > should have twice, second time because of the received character > these too lines that repeat indefinitely, the interrupt not coming. > although interrupts are enabled at PIC level] > > I use the "XT-PIC-XT" (8259A) interrupt controller. As far as I know, > Linux sets up the controller to "edge triggering", but uses > "handle_level_irq" for it. When received by Xenomai, the interrupt is > masked and acked at PIC level ( "ack" means EOI at 8259A). When the > interrupt handling in the program finishes, it unmasks the interrupt. I > verified that my 8259A has a latch that can detect the UART interrupt > even if masked, so that when unmasked again, it can be delivered. Try to pass I_EDGE to rt_intr_create. The UART IRQs are edge-triggered, so you have to enable the appropriate handling at kernel IRQ handler level. Jan
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