Hi Patrice,
OK. Please, verify first that you can boot µClinux without Xenomai on
your board with the 2 extra hrtimer and hrclock peripherals.
There is no priority on IRQ with NIOS.
So, If I have understood, I could put:
IRO = 7 for hrtimer
IRQ = 8 for hrclock
IRQ = 1 for sys_clk_timer
with this configuration µClinux without Xenomai with the 2 extra hrtimer and
hrclock peripherals can boot on the board .
But I'm wondering why with the first configuration (IRO = 1 for hrtimer,IRQ = 2
for hrclock and IRQ = 3 for sys_clk_timer), it didn't boot?
Please verify that you have correctly enabled all the right options
under SOPC builder for hrtimer and hrclock.
Because we have flexibility in HW configuration with SoPC, we must be more
careful.
Configuration of hrtimer with the SoPC Builder:
• Timer: 32 bits.
• Timeout period: 1 µs.
• Preset : custom. Writable period, readable snapshot, Start/Stop control bits.
Configuration of hrclock with the SoPC Builder:
in the snapshot mode. Its configuration with the SoPC Builder tool is:
• 64-bit timer.
• Timeout period: 5 clocks. clock=20 ns (100 ns). The timer functionality is
not used by Xenomai.
• Preset: custom. Writable period, readable snapshot, Start/Stop control bits.
Is it correct?
According to errno.h, code -19 is ENODEV, please verify your timer
configuration and respect naming convention
Here, you speek about "sys_clock_timer"?
Configuration of sys_clock_timer with the SoPC Builder:
• 32-bit timer.
• Timeout period: 10 ms.
• Preset: custom. Writable period, readable snapshot, Start/Stop control bits.
Regards,
#ifndef __NIOS2_H__
#define __NIOS2_H__
/*
* This file contains hardware information about the target platform.
*
* This file is automatically generated. Do not modify.
*/
/* Input System: std_1s40 */
/* Target CPU: cpu */
/* Nios II Constants */
#define NIOS2_STATUS_PIE_MSK 0x1
#define NIOS2_STATUS_PIE_OFST 0
#define NIOS2_STATUS_U_MSK 0x2
#define NIOS2_STATUS_U_OFST 1
/*
* Outputting basic values from system.ptf.
*/
#define na_pll 0x008108c0
#define na_pll_clock_freq 50000000
#define na_ext_ram_bus_clock_freq 50000000
#define na_ext_flash 0000000000
#define na_ext_flash_size 0x00800000
#define na_ext_flash_end 0x00800000
#define na_ext_flash_clock_freq 50000000
#define na_ext_ram 0x02000000
#define na_ext_ram_size 0x00100000
#define na_ext_ram_end 0x02100000
#define na_ext_ram_clock_freq 50000000
#define na_onchip_ram_64_kbytes 0x02100000
#define na_onchip_ram_64_kbytes_size 0x00010000
#define na_onchip_ram_64_kbytes_end 0x02110000
#define na_onchip_ram_64_kbytes_clock_freq 50000000
#define na_onchip_ram_64_kbytes_s1 0x02100000
#define na_lan91c111 0x00800000
#define na_lan91c111_irq 7
#define na_lan91c111_clock_freq 50000000
#define na_sys_clk_timer 0x00810800
#define na_sys_clk_timer_irq 3
#define na_sys_clk_timer_clock_freq 50000000
#define na_jtag_uart 0x00810820
#define na_jtag_uart_irq 4
#define na_jtag_uart_clock_freq 50000000
#define na_uart1 0x00810840
#define na_uart1_irq 5
#define na_uart1_clock_freq 50000000
#define na_button_pio 0x00810830
#define na_button_pio_irq 6
#define na_button_pio_clock_freq 50000000
#define na_led_pio 0x00810880
#define na_led_pio_clock_freq 50000000
#define na_seven_seg_pio 0x00810890
#define na_seven_seg_pio_clock_freq 50000000
#define na_reconfig_request_pio 0x008108a0
#define na_reconfig_request_pio_clock_freq 50000000
#define na_sdram 0x01000000
#define na_sdram_size 0x01000000
#define na_sdram_end 0x02000000
#define na_sdram_clock_freq 50000000
#define na_sysid 0x00810828
#define na_sysid_clock_freq 50000000
#define na_lcd_display 0x008108b0
#define na_lcd_display_clock_freq 50000000
#define na_hrtimer 0x00810860
#define na_hrtimer_irq 1
#define na_hrtimer_clock_freq 50000000
#define na_hrclock 0x00810900
#define na_hrclock_irq 2
#define na_hrclock_clock_freq 50000000
#define na_uart_0 0x008108e0
#define na_uart_0_irq 8
#define na_uart_0_clock_freq 50000000
/* Executing ...scripts/nios2.h/altera_avalon_lan91c111.pm */
/* Redefining lan91c111 -> enet */
#undef na_lan91c111
#undef na_lan91c111_irq
#define na_enet 0x00800000
#define na_enet_irq 7
#define LAN91C111_REGISTERS_OFFSET 768
#define LAN91C111_DATA_BUS_WIDTH 32
/* Executing ...scripts/nios2.h/altera_avalon_timer.pm */
/* system timer input clock frequency */
#define nasys_clock_freq 50000000
#define nasys_clock_freq_1000 50000
/* Redefining sys_clk_timer -> timer0 */
#undef na_sys_clk_timer
#undef na_sys_clk_timer_irq
#define na_timer0 ((void *) 0x00810800)
#define na_timer0_irq 3
/* Executing ...scripts/nios2.h/altera_avalon_jtag_uart.pm */
/* No translation necessary for jtag_uart */
/* Executing ...scripts/nios2.h/altera_avalon_uart.pm */
/* Redefining uart1 -> uart0 */
#undef na_uart1
#undef na_uart1_irq
#define na_uart0 ((void **) 0x00810840)
#define na_uart0_irq 5
/* The default uart is always the first one found in the PTF file */
#define nasys_printf_uart na_uart0
/* Redefining uart_0 -> uart1 */
#undef na_uart_0
#undef na_uart_0_irq
#define na_uart1 ((void **) 0x008108e0)
#define na_uart1_irq 8
/* Executing ...scripts/nios2.h/altera_avalon_pio.pm */
#ifndef __ASSEMBLY__
#include <asm/pio_struct.h>
#endif
/* Casting base addresses to the appropriate structure */
#undef na_button_pio
#undef na_button_pio_irq
#define na_button_pio ((np_pio*) 0x00810830)
#define na_button_pio_irq 6
/* Casting base addresses to the appropriate structure */
#undef na_led_pio
#define na_led_pio ((np_pio*) 0x00810880)
/* Casting base addresses to the appropriate structure */
#undef na_seven_seg_pio
#define na_seven_seg_pio ((np_pio*) 0x00810890)
/* Casting base addresses to the appropriate structure */
#undef na_reconfig_request_pio
#define na_reconfig_request_pio ((np_pio*) 0x008108a0)
/* Executing ...scripts/nios2.h/altera_avalon_sysid.pm */
/* No translation necessary for sysid */
/*
* Basic System Information
*/
#define nasys_icache_size 4096
#define nasys_icache_line_size 32
#define nasys_dcache_size 0
#define nasys_dcache_line_size 0
#define nasys_program_mem na_sdram
#define nasys_program_mem_size na_sdram_size
#define nasys_program_mem_end na_sdram_end
#define na_cpu_clock_freq 50000000
#define CPU_RESET_ADDRESS 0000000000
#define CPU_EXCEPT_ADDRESS 0x01000020
#endif /* __NIOS2_H__ */
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