On 17/06/10 11:07, Daniele Nicolodi wrote:
> No. I'm running a continuous memory mapped acquisition. The only maybe
> uncommon thing I'm doing is that I'm reading the mmapped buffer in fixed
> chunks, rather than reading all the samples available each time. The
> number of samples I read each time is larger than the 4095 samples after
> which the hardware sends the FIFO half full trigger event.
I modified my code from a loop like:
unsigned int required = <compute required number of bytes>;
unsigned int read = 0;
void * buffer = a4l_mmap(dsc, ...);
while (1) {
while (read < required) {
read = a4l_pool(...);
clock_nanosleep(...);
}
process(buffer, ...);
a4l_buff_markrw(dsc, subdevice, required, ...);
}
to something like:
unsigned int required = <compute required number of bytes>;
unsigned int read = 0;
void *buffer = malloc(required);
while (1) {
while (read < required) {
a4l_sys_read(dsc, buffer + read, required - read);
}
process(buffer, ...);
}
I tested this setup over the weekend and the wrong samples went away!
Therefore i suspect that the problem is not related to FIFO
synchronization but to kernel space buffer handling.
I have tried to look at Analogy buffer handling, but the lack of any
comment in the source code makes understanding how it is supposed to
work a complex task.
Alexis, can you see any case where there may be a synchronization issue
like the one I'm seeing in your code? Any suggestion in where to look
for the bug?
Thanks. Cheers,
--
Daniele
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