Da: Gilles Chanteperdrix [[email protected]]
Inviato: sabato 15 dicembre 2012 15.54
> Anyway, I also asked you to run the "tsc" test, what does this test tell
> you?
In the structure tsc_info must assign addresses (phy and virt) of timer
assigned to clocksource or clockevent?
I have assigned the offset of timer assigned to clockevent (base address is the
same because the timer is 64-bit)
static void l138_xenomai_tsc_init(void)
{
struct davinci_soc_info *soc_info = &davinci_soc_info;
struct davinci_timer_instance *dtip = soc_info->timer_info->timers;
void __iomem *base;
base = ioremap(dtip[0].base, SZ_4K);
tsc_info.type = IPIPE_TSC_TYPE_FREERUNNING;
tsc_info.freq = l138_clock_tick_rate;
tsc_info.counter_vaddr = (unsigned long)(base + TIM12);
tsc_info.u.counter_paddr = dtip[0].base + TIM12;
tsc_info.u.fr.mask = 0xffffffff;
__ipipe_tsc_register(&tsc_info);
}
and in the board declaration:
static struct davinci_timer_instance da850_timer_instance[4] = {
{
.base = DA8XX_TIMER64P0_BASE,
.bottom_irq = IRQ_DA8XX_TINT12_0,
.top_irq = IRQ_DA8XX_TINT34_0,
},
{
.base = DA8XX_TIMER64P1_BASE,
.bottom_irq = IRQ_DA8XX_TINT12_1,
.top_irq = IRQ_DA8XX_TINT34_1,
},
{
.base = DA850_TIMER64P2_BASE,
.bottom_irq = IRQ_DA850_TINT12_2,
.top_irq = IRQ_DA850_TINT34_2,
},
{
.base = DA850_TIMER64P3_BASE,
.bottom_irq = IRQ_DA850_TINT12_3,
.top_irq = IRQ_DA850_TINT34_3,
},
};
Result not change
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