On 01/14/2013 11:27 AM, Stefan Roese wrote:
> Hi Matthew,
>
> On 01/12/2013 06:21 PM, [email protected] wrote:
>> I'm looking for recommendations on how to best port ipipe support to a
>> new ARM SoC. The SoC has started to show up in mainline, but many of
>> the features haven't made it over yet. Xilinx maintains a git repo
>> here:
>>
>> git://git.xilinx.com/linux-xlnx.git
>>
>> And it look like they've synced with mainline 3.6
>>
>> The two approaches I've considered were either trying to port ipipe to
>> stock 3.6 (or at least the generic and ARM bits) or trying to backport
>> the Xilinx code to 3.5.3. I started with the later approach, but some
>> changes to the common clock architecture between 3.5 and 3.6 make this
>> somewhat difficult.
>>
>> Any thoughts on which approach would be better?
>
> I'm also working on supporting Zynq in I-pipe. My approach was to use
> the Xilinx 3.5.0 code version (git tag "xilinx-14.3-build2"). And port
> the I-pipe version from Gilles git repository to it. I still need to do
> some cleanup then I can send you the latest version.
Hi Stefan, Matthew,
I do not know if you managed to get the I-pipe working on Zynq.
You may have missed it, but it may be very important for debugging the
issues you encounter with the I-pipe port on Zynq, printk from primary
domain in I-pipe patches for Linux 3.4 and 3.5 does not work. So, if
you are debugging with printk, it may lead you to false conclusions.
You should apply the following patch (it has been pushed in the
for-core-3.5.7 branch of the ipipe-gch git):
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 3b86167..f77ef11 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -440,7 +440,7 @@ void __ipipe_ipis_alloc(void)
return;
/* __ipipe_first_ipi is 0 here */
- ipi_nr = IPI_IPIPE_FIRST + IPIPE_LAST_IPI;
+ ipi_nr = IPI_IPIPE_FIRST + IPIPE_LAST_IPI + 1;
for (virq = IPIPE_IPI_BASE; virq < IPIPE_IPI_BASE + ipi_nr; virq++) {
_virq = ipipe_alloc_virq();
--
Gilles.
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