I really had *hoped* that a possibility to probe a hardware register existed...
Egbert Eich schrieb:
[EMAIL PROTECTED] writes:
> > That has been months ago. Now: one problem solved, others remaining :)
> I got the source, was then 4.2.99-4, but I was too lazy and too scared > (being a non-coder) to change a thing for quite a long time.
> Now I'm proud to present the attached almost-no-brainer.
> It gives me a [EMAIL PROTECTED] mode with 16 bpp, that was unavailable > before.It's tested on a laptop with 1024x768 pixels screen and ct65554 > chipset @ 4 MB. It's still to be tested for the other HiQv chipsets.
> BTW, has anybody SEEN a ct68554?
This chip seems to exist. However noone working on the driver ever had access to one.
Your patch was almost correct. There is actually a register where one can check if the bus is 32 or 64bit. Please try patch below.
Egbert.
------------------------------------------------------------------------
Index: ct_driver.c
===================================================================
RCS file: /home/eich/cvs/xc/programs/Xserver/hw/xfree86/drivers/chips/ct_driver.c,v
retrieving revision 1.1.1.44
diff -u -r1.1.1.44 ct_driver.c
--- ct_driver.c 6 Aug 2003 16:23:42 -0000 1.1.1.44
+++ ct_driver.c 18 Aug 2003 19:32:26 -0000
@@ -1767,10 +1767,12 @@
case CHIPS_CT69030:
/* The ct69030 has 4Mb of SGRAM integrated */
pScrn->videoRam = 4096;
+ cPtr->Flags |= Chips64BitMemory;
break;
case CHIPS_CT69000:
/* The ct69000 has 2Mb of SGRAM integrated */
pScrn->videoRam = 2048;
+ cPtr->Flags |= Chips64BitMemory;
break;
case CHIPS_CT65550:
/* XR43: DRAM interface */
@@ -1819,6 +1821,13 @@
pScrn->videoRam = 1024;
break;
}
+ /* XR43: DRAM interface */
+ /* bit 4-5 mem interface width */
+ /* 00: 32Bit */
+ /* 01: 64Bit */
+ tmp = cPtr->readXR(cPtr, 0x43);
+ if ((tmp & 0x10) == 0x10)
+ cPtr->Flags |= Chips64BitMemory;
break;
}
}
@@ -2270,9 +2279,9 @@
/* Check if maxClock is limited by the MemClk. Only 70% to allow for */
/* RAS/CAS. Extra byte per memory clock needed if framebuffer used */
/* Extra byte if the overlay plane is activated */
- /* We have a 64bit wide memory bus on the 69030 and 69000, and 32bits */
- /* on the others. Thus multiply by a suitable factor */ - if ((cPtr->Chipset == CHIPS_CT69030) || (cPtr->Chipset == CHIPS_CT69000)) {
+ /* If flag Chips64BitMemory is set assume a 64bitmemory interface, */
+ /* and 32bits on the others. Thus multiply by a suitable factor */ + if (cPtr->Flags & Chips64BitMemory) {
if (cPtr->FrameBufferSize && (cPtr->PanelType & ChipsLCD))
if (cPtr->Flags & ChipsOverlay8plus16 )
cPtr->MaxClock = min(cPtr->MaxClock, MemClk->Clk * 8 * 0.7 / 4);
Index: ct_driver.h
===================================================================
RCS file: /home/eich/cvs/xc/programs/Xserver/hw/xfree86/drivers/chips/ct_driver.h,v
retrieving revision 1.1.1.7
diff -u -r1.1.1.7 ct_driver.h
--- ct_driver.h 4 Feb 2002 10:09:08 -0000 1.1.1.7
+++ ct_driver.h 18 Aug 2003 19:32:26 -0000
@@ -108,6 +108,7 @@
#define ChipsVideoSupport 0x00000100
#define ChipsDualChannelSupport 0x00000200
#define ChipsDualRefresh 0x00000400
+#define Chips64BitMemory 0x00000800
/* Options flags for the C&T chipsets */
#define ChipsHWCursor 0x00001000
Good night from ol' Europe. wij
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