Hi Michael,
> Sent: Monday, January 02, 2017 at 11:02 AM
> From: Michael <[email protected]>
> To: "Kevin Brace" <[email protected]>
> Cc: [email protected], CK <[email protected]>
> Subject: Re: VT8623 [Apollo CLE266]
>
> Hello,
>
> Stupid question - why restrict yourself to old kernels and Xservers?
> We've got relatively recent Xorg ( 1.18 ) running, with acceleration,
> on things like 32bit Suns.
> Also, I kinda doubt that any C3 boards could take enough memory to make
> PAE useful - or am I missing something here?
>
> have fun
> Michael
>
While it is not necessary, I try to maintain backward compatibility since it is
not that difficult to do so.
This is one major reason why I still use Ubuntu 10.04 for testing purposes.
As a result, I believe the current OpenChrome (Version 0.5) can be compiled for
X.Org Server 1.7 (the version used with Ubuntu 10.04 LTS if I am correct) all
the way to 1.15.
With the latest fixes I have put in for the future Version 0.6, it should
compile against X.Org Server 1.19.
Another reason is that I have not personally tried Gentoo or Arch Linux so far.
(I will someday.)
I will have to use Gentoo or Arch Linux someday since I will need to test the
next generation OpenChrome DRM with Linux 3.19-rc6 kernel I use for development
purpose against CLE266 chipset.
While this is not really related to CLE266 chipset per se, but VIA
Technologies C3 processor was originally going to be called WinChip 4 processor.
https://www.ele.uva.es/~jesman/BigSeti/ftp/Cajon_Desastre/MPR/121605.pdf
For marketing reasons, Centaur Technology (they apparently still exist in
Austin, TX) changed the bus interface of WinChip 4 from Socket 7 (something AMD
used) to Socket 370 (P6 bus) when IDT sold Centaur Technology to VIA
Technologies for about $50 million around Year 1999.
Since WinChip 4 was originally supposed to be a Socket 7 processor (like
AMD-K6-2 processor), they never had PAE implemented since Socket 7 does not
have those extra 4 address bits exposed (basically, A[35:32]), if my memory
serves me correctly.
VIA Technologies did a major refresh of C3 processor once, and if I am correct,
it was codenamed Nehemiah. (Centaur Technology codename was C5XL,)
They did implement CMOV instructions if I am correct, and probably implemented
4MB page size.
But you are right, C3 will never use more than 4 GB of RAM, so they probably
thought implementing PAE was not necessary at that time. (early Year 2000)
Regards,
Kevin Brace
The OpenChrome Project maintainer / developer
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