On Jan 13, 09 18:39:10 +0100, Xavier Bestel wrote: > > Because the chip might reorder memory writes, and decide for later > > blocks to be pushed out first (or even pushed out to memory w/o changing > > the cache). That way you *could* see multiple tearings. > > I thought a cache flush acted like a barrier, i.e. even if reordered > between them all writes before the flush should go.
Yes, but the beam could already in the middle of the screen if you flush only at the end of all blocks. Matthias -- Matthias Hopf <[email protected]> __ __ __ Maxfeldstr. 5 / 90409 Nuernberg (_ | | (_ |__ [email protected] Phone +49-911-74053-715 __) |_| __) |__ R & D www.mshopf.de _______________________________________________ xorg-driver-ati mailing list [email protected] http://lists.x.org/mailman/listinfo/xorg-driver-ati
