http://bugs.freedesktop.org/show_bug.cgi?id=18397
--- Comment #81 from Daniel Vetter <[email protected]> 2009-10-27 08:18:56 PST --- > --- Comment #72 from Dave Airlie <[email protected]> 2009-08-26 > 04:31:27 PST --- > this is written in some unspecified docs, however 2 has never made sense to > me. > > 1. After BITBLT_MULTI copy data from frame buffer to system memory, flush > entire 2D pixel cache and > wait for 2D engine idle and clean to ensure the copied data to arrive into > bus controller. > 2. Copy the last pixel back to frame buffer from system memory to flush data > out of bus controller to system > physical memory. > 3. Wait for flush process to be completed. This is done by either waiting for > engine idle or using timestamp > write back mechanism. Just my 2 cents. Number 2 makes sense to me: When you write from dev A to dev B and want to ensure that all the writes have arrived in B, you need to read from B to A. Because PCI specifies that a read flushes all write cashes (in the other direction) on its path, this flushes all outstanding writes to B. Usually A=CPU/main memory and B=device and one uses a read of a side-effect free reg, but it should work the other way round, too. -- Configure bugmail: http://bugs.freedesktop.org/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are the assignee for the bug. _______________________________________________ xorg-driver-ati mailing list [email protected] http://lists.x.org/mailman/listinfo/xorg-driver-ati
