r6xx hardware requires at least 4 dw alignment to work around a hw bug. Align to 8 dw to align with CP fetch sizes on all asics.
v2: align to 8 DWs, apply to all asics Signed-off-by: Alex Deucher <[email protected]> --- src/radeon_kms.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/radeon_kms.c b/src/radeon_kms.c index 82e88d4..3a1dbcd 100644 --- a/src/radeon_kms.c +++ b/src/radeon_kms.c @@ -100,6 +100,12 @@ void radeon_cs_flush_indirect(ScrnInfoPtr pScrn) info->accel_state->cbuf.vb_start_op = -1; } + /* pad the IB to a multiple of 8 dwords to align with CP fetch requirements + * R6xx requires at least 4 dword alignment to work around a hw bug + */ + while (info->cs->cdw & 7) + radeon_cs_write_dword(info->cs, 0x80000000); + radeon_cs_emit(info->cs); radeon_cs_erase(info->cs); -- 1.8.3.1 _______________________________________________ xorg-driver-ati mailing list [email protected] http://lists.x.org/mailman/listinfo/xorg-driver-ati
