On Mon, Oct 20, 2014 at 3:01 PM, David Harks <[email protected]> wrote: > > On Oct 20, 2014, at 1:09 PM, Alex Deucher <[email protected]> wrote: > > On Fri, Oct 17, 2014 at 7:36 PM, David Harks <[email protected]> wrote: > > All, > > In the proprietary driver, it’s possible to set the colorspace used for > output, with 4 possible options on my hardware: YCbCr 4:4:4, YCbCr 2:2:2, > RGB Limited, and RGB Full. For a system I’m working on, we have been using > the YCbCr 4:4:4 color space for compatibility reasons with some of the > devices we output to, and I’d like to get the same feature going on the > radeon driver. > > From what I’ve read > (http://lists.freedesktop.org/archives/xorg/2014-March/056478.html), this > feature isn’t yet part of the radeon driver, but since it seems to be a > register setting it may be possible to add. So I took a look at the code in > dce5_crtc_load_lut() and modified it to use NI_OUTPUT_CSC_YCBCR_709, > compiled, and tried it. > > It didn’t seem to change the output at all. > > So I grabbed a copy of radeontool, and tried to see if I could inspect the > registers to see if my changes were taking effect, but I think I’m missing > something because the values I get don’t seem to be what I’d expect: > > avivotool regmatch 0x68f0 # NI_OUTPUT_CSC_CONTROL + > radeon_crtc->crtc_offset > 0x68f0 0x01000020 (16777248) > > I would expect the output to be something with 0x33, since > (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_YCBCR_709) | > NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_YCBCR_709)) should be 0x33. > > Is there some other register I might need to touch in order to make these > changes take effect? Any pointers to what else I should be looking for? > > > What asic are you using? Note that register bar moved on Sea Islands > and newer asics and I'm not sure if the version of avivotool you are > using handles that correctly yet. Also note that these registers are > instanced (hence the radeon_crtc->crtc_offset being added to the > register offset), so make sure you are reading the appropriate > instance for the display controller you are using. > > > it’s an AMD E2-1800 APU, AKA a Radeon HD 7340 (Wrestler), which I think gets > classified as a PALM. So I suppose it actually falls under the “Evergreen” > moniker, which branches to the dce4_crtc_load_lut() code, which in turn > looks to have a completely different machinery for this purpose, if any. > > Under reg_srcs/evergreen, I see a CB_COLOR_CONTROL entry, but that’s just a > wild guess. Any pointers to where else I should be looking?
I think it was a little more complex on DCE4. I'll have to try and dig up the info and get back to you. The CB_* registers are part of the 3D pipeline rather than the display pipe so they are not relevant here. Alex _______________________________________________ xorg-driver-ati mailing list [email protected] http://lists.x.org/mailman/listinfo/xorg-driver-ati
