Bruce Simpson wrote:
> Thanks for clarifying that BGP itself would be used as the mechanism for
> dividing BGP's work across cores. This is likely to be easier to deal
> with, and it's something that can probably achieved in your time frame.
>
This might be useful:
http://www.cs.uiuc.edu/homes/caesar/papers/hair.pdf
http://www.seas.upenn.edu/~kiderj/research/papers/APSP-gh08-fin-T.pdf
They're discussing hardware implementation of BGP design elements on
GPGPU and FPGA, however this is highly dependent on memory layout, and
specific operations the GPU can offer. It might supply some general
ideas to draw on though.
cheers,
BMS
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