On Tue, 4 Sep 2001, Rick Scott wrote:
> Okay, back to it....
>
> I added an INPLL(pScrn, R128_VCLK_ECP_CNTL) to the trace in
> R128SavePLLRegisters and R128RestorePLLRegisters. In the initial save this
> register is 0x00000002, after the new mode is setup, it is still 0x00000002. I
> did however notice that R128_PPLL_CNTL is getting set to 0x00000000, but during
> server exit, when the original mode is restored, it is being set to 0x00000001.
> What does R128_PPLL_CNTL do?? It would appear to be something to do with a
This setting resets it.. It is interesting that the value is not the
default one, though, of course, my documentation does not explain what the
default value does.
Can I ask you to mail me the complete dump of PLL registers after the
server starts up and during boot ?
thanks !
Vladimir Dergachev
PS If you want I can mail you (off the list) a small utility to do that.
> reset...
>
> >From what I can see R128_VCLK_ECP_CNTL is not referenced in the driver at all.
>
>
> On 1-Sep-01 at 13:31, [EMAIL PROTECTED] ([EMAIL PROTECTED]) wrote:
> >
> > Can you check whether VCLK_ECP_CNTL (pll register 0x0008) is set right ?
> > (0x0 is not the right value..) It is responsible for choosing which clock
> > is used for video clock.
> >
> > Vladimir Dergachev
> >
> > On Sun, 26 Aug 2001, Rick Scott wrote:
> >
> > > (--) R128(0): Chipset: "ATI Rage 128 Pro ULTRA TF (AGP)" (ChipID =
> > > 0x5446)
> > > A little more info that will hopefully convince someone that this card is
> > > not being handled correctly. When the machine boots, both the monitor and
> > > TV-Out display a nice image. When X starts up the image gets messed up.
> > > Killing the X server restores a nice image, so I assume the save and
> > > restore of the CRTC and PLL regs is working well. While the server is
> > > running, I measure the horizontal sync rate on the monitor connector, and
> > > it is _not_ what the driver thinks it calculated. So I had the driver
> > > print out the regs as it is saving them the first time, hoping that I
> > > could work out the equation that is being used. The following is what I
> > > get ....
> > > The CRTC numbers that get saved are...
> > > crtc_h_total_disp = 0x004f0060
> > > crtc_v_total_disp = 0x018f020b
> > >
> > > If my calculations are correct, gives a display size of 640x400 with the
> > > overall sizes of 776x524. By putting a scope on the horizontal sync line
> > > of the monitor connector, I measure 31.5 kHz, which would mean a dot
> > > clock of 24.444 MHz.
> > >
> > > The PLL numbers that get saved are...
> > > ppll_ref_div = 0x0000003c
> > > ppll_div_3 = 0x00040116
> > >
> > > According to the r128_driver source, this would be a post_div of 3, which
> > > would make the PLL output 73.332 MHz. Now, if I'm reading everything
> > > correct, I should be able to take the PLL output freq, divide by 278
> > > (0x116) and multiply by 60 (0x3c) and get the PLL reference freq, which
> > > is 27 MHz.
> > > (II) R128(0): PLL parameters: rf=2700 rd=60 min=12500 max=35000;
> > > xclk=13400
> > > So you do the math, and end up with 15.827 MHz, which is not 27 MHz.
> > >
> > > So I think that is fairly good proof that the PLL on this card is
> > > different than all the others. I'm willing and able to help get this
> > > fixed, but according to ATI I have to be an XFree developer to get more
> > > info, and according to XFree I have to supply a patch to fix something
> > > before that can happen. The only thing I can see that needs fixing is
> > > related to the hardware of this card, so I'm screwed. I can't get the info
> > > I need to submit a patch, and I can't submit a patch because I don't have
> > > the info I need :(
> > >
> > > By manipulating the post_div bits that get written to the card, I'm
> > > pretty sure they are doing what the driver thinks, but I haven't been
> > > able to come up with an equation that makes the rest of the numbers match.
> > >
> > > There must be someone out there with the needed info.
> > >
> > >
> > > _______________________________________________
> > > Xpert mailing list
> > > [EMAIL PROTECTED]
> > > http://XFree86.Org/mailman/listinfo/xpert
> > >
>
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