On Mon, 12 Nov 2001, Eugene M. Kim wrote:
> >
> > Any load or store on uncached memory (like the graphics accelerator's
> > registers) will flush it.
> >
> > Any locked atomic RMW instruction (xchgl).
> >
> > Any port IO (write 0x3D0 or other unused port address. Expensive).
>
> Thank you for the information. I also read about these in the IA-32
> documentation, and supposed there would be no problem because in order
> to initiate the blit we have to tell the GC through the memory-mapped
> I/O range (uncached). However it didn't work out as expected, and the
> same Intel documentation also said serializing instructions would not
> push data out of the write cache to the external memory, so I was
> wondering if there were some other ways.
>
Perhaps the problem isn't what you think it is. The i810 driver
doesn't seem to have any problems with this and I believe its DMA
buffer is write combined.
Mark.
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