Use the version in cvs right now, or use the attatched patch against 4.2.0
nv driver.
ani
On Sat, 20 Apr 2002, Richard Chan wrote:
> Folks,
>
> Using XFree86 4.2 with nv driver on G4 PowerMAC with Nvidia GeForce2/MX card (VGA
>and ADC)
> Debian Linux Woody, 2.4.18-newpmac kernel
>
> Everything works great with VGA out or text console on ADC and XFree86 on VGA -
>however
> I just can't figure out how to get XFree86 appearing on the ADC output ( with an
>Apple Studio
> Display 17" CRT - not the current LCD display offerings).
>
> Is there some special nv Option or is this a "known problem" with Apple's
>proprietary stuff.
>
> Thanks for any enlightenment.
>
> Richard
>
diff -uNr nv.orig/nv_cursor.c nv/nv_cursor.c
--- nv.orig/nv_cursor.c Mon Feb 25 22:54:49 2002
+++ nv/nv_cursor.c Mon Feb 25 22:54:45 2002
@@ -109,7 +109,7 @@
NVPtr pNv = NVPTR(pScrn);
pNv->riva.ShowHideCursor(&pNv->riva, 0);
- *(pNv->riva.CURSORPOS) = (x & 0xFFFF) | (y << 16);
+ pNv->riva.PRAMDAC[0x0000300/4] = (x & 0xFFFF) | (y << 16);
pNv->riva.ShowHideCursor(&pNv->riva, 1);
}
@@ -123,8 +123,10 @@
back = ConvertToRGB555(bg);
#if X_BYTE_ORDER == X_BIG_ENDIAN
- fore = (fore << 8) | (fore >> 8);
- back = (back << 8) | (back >> 8);
+ if((pNv->Chipset & 0x0ff0) == 0x0110) {
+ fore = (fore << 8) | (fore >> 8);
+ back = (back << 8) | (back >> 8);
+ }
#endif
if (pNv->curFg != fore || pNv->curBg != back) {
diff -uNr nv.orig/nv_dac.c nv/nv_dac.c
--- nv.orig/nv_dac.c Mon Feb 25 22:54:49 2002
+++ nv/nv_dac.c Mon Feb 25 22:54:45 2002
@@ -71,6 +71,15 @@
if(mode->Flags & V_INTERLACE)
vertTotal |= 1;
+ if(pNv->FlatPanel) {
+ vertStart = vertTotal - 3;
+ vertEnd = vertTotal - 2;
+ vertBlankStart = vertStart;
+ horizStart = horizTotal - 3;
+ horizEnd = horizTotal - 2;
+ horizBlankEnd = horizTotal + 4;
+ }
+
pVga->CRTC[0x0] = Set8Bits(horizTotal);
pVga->CRTC[0x1] = Set8Bits(horizDisplay);
pVga->CRTC[0x2] = Set8Bits(horizBlankStart);
@@ -147,6 +156,8 @@
if(pNv->riva.Architecture >= NV_ARCH_10)
pNv->riva.CURSOR = (U032 *)(pNv->FbStart + pNv->riva.CursorStart);
+ pNv->riva.LockUnlock(&pNv->riva, 0);
+
pNv->riva.CalcStateExt(&pNv->riva,
nvReg,
i,
@@ -156,6 +167,24 @@
mode->Clock,
mode->Flags);
+ nvReg->scale = pNv->riva.PRAMDAC[0x00000848/4] & 0xfff000ff;
+ if(pNv->FlatPanel) {
+ nvReg->pixel |= (1 << 7);
+ nvReg->scale |= (1 << 8) ;
+ }
+ if(pNv->SecondCRTC) {
+ nvReg->head = 0;
+ nvReg->head2 = 0x00001111;
+ nvReg->crtcOwner = 3;
+ nvReg->pllsel |= 0x20000800;
+ nvReg->vpll2 = nvReg->vpll;
+ } else {
+ nvReg->head = 0x00001111;
+ nvReg->head2 = 0;
+ nvReg->crtcOwner = 0;
+ nvReg->vpll2 = pNv->riva.PRAMDAC0[0x00000520/4];
+ }
+
return (TRUE);
}
@@ -184,8 +213,17 @@
{
NVPtr pNv = NVPTR(pScrn);
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NVDACSave\n"));
- vgaHWSave(pScrn, vgaReg, VGA_SR_MODE | (saveFonts? VGA_SR_FONTS : 0));
+
+#if defined(__powerpc__)
+ saveFonts = FALSE;
+#endif
+
+ vgaHWSave(pScrn, vgaReg, VGA_SR_CMAP | VGA_SR_MODE |
+ (saveFonts? VGA_SR_FONTS : 0));
pNv->riva.UnloadStateExt(&pNv->riva, nvReg);
+
+ if((pNv->Chipset & 0x0ff0) == 0x0110)
+ nvReg->crtcOwner = ((pNv->Chipset & 0x0fff) == 0x0112) ? 3 : 0;
}
#define DEPTH_SHIFT(val, w) ((val << (8 - w)) | (val >> ((w << 1) - 8)))
diff -uNr nv.orig/nv_dga.c nv/nv_dga.c
--- nv.orig/nv_dga.c Mon Feb 25 22:54:49 2002
+++ nv/nv_dga.c Mon Feb 25 22:54:45 2002
@@ -234,8 +234,8 @@
NVAdjustFrame(pScrn->pScreen->myNum, x, y, flags);
- while(pNv->riva.PCIO[0x3da] & 0x08);
- while(!(pNv->riva.PCIO[0x3da] & 0x08));
+ while(VGA_RD08(pNv->riva.PCIO, 0x3da) & 0x08);
+ while(!(VGA_RD08(pNv->riva.PCIO, 0x3da) & 0x08));
pNv->DGAViewportStatus = 0;
}
diff -uNr nv.orig/nv_driver.c nv/nv_driver.c
--- nv.orig/nv_driver.c Mon Feb 25 22:54:49 2002
+++ nv/nv_driver.c Mon Feb 25 22:54:45 2002
@@ -179,13 +179,11 @@
"vgaHWGetHWRec",
"vgaHWGetIndex",
"vgaHWInit",
- "vgaHWLock",
"vgaHWMapMem",
"vgaHWProtect",
"vgaHWRestore",
"vgaHWSave",
"vgaHWSaveScreen",
- "vgaHWUnlock",
"vgaHWddc1SetSpeed",
NULL
};
@@ -305,7 +303,8 @@
OPTION_FBDEV,
OPTION_ROTATE,
OPTION_VIDEO_KEY,
- OPTION_FLAT_PANEL
+ OPTION_FLAT_PANEL,
+ OPTION_CRTC_NUMBER
} NVOpts;
@@ -319,6 +318,7 @@
{ OPTION_ROTATE, "Rotate", OPTV_ANYSTR, {0}, FALSE },
{ OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE },
{ OPTION_FLAT_PANEL, "FlatPanel", OPTV_BOOLEAN, {0}, FALSE },
+ { OPTION_CRTC_NUMBER, "CrtcNumber", OPTV_INTEGER, {0}, FALSE },
{ -1, NULL, OPTV_NONE, {0}, FALSE }
};
@@ -565,13 +565,9 @@
NVEnterVT(int scrnIndex, int flags)
{
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
- NVPtr pNv = NVPTR(pScrn);
- vgaHWPtr hwp = VGAHWPTR(pScrn);
DEBUG(xf86DrvMsg(scrnIndex, X_INFO, "NVEnterVT\n"));
- vgaHWUnlock(hwp);
- pNv->riva.LockUnlock(&pNv->riva, 0);
if (!NVModeInit(pScrn, pScrn->currentMode))
return FALSE;
NVAdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0);
@@ -600,13 +596,11 @@
{
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
NVPtr pNv = NVPTR(pScrn);
- vgaHWPtr hwp = VGAHWPTR(pScrn);
DEBUG(xf86DrvMsg(scrnIndex, X_INFO, "NVLeaveVT\n"));
NVRestore(pScrn);
pNv->riva.LockUnlock(&pNv->riva, 1);
- vgaHWLock(hwp);
}
@@ -645,7 +639,6 @@
NVCloseScreen(int scrnIndex, ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
- vgaHWPtr hwp = VGAHWPTR(pScrn);
NVPtr pNv = NVPTR(pScrn);
DEBUG(xf86DrvMsg(scrnIndex, X_INFO, "NVCloseScreen\n"));
@@ -653,7 +646,6 @@
if (pScrn->vtSema) {
NVRestore(pScrn);
pNv->riva.LockUnlock(&pNv->riva, 1);
- vgaHWLock(hwp);
}
NVUnmapMem(pScrn);
@@ -782,12 +774,10 @@
static xf86MonPtr
NVdoDDC(ScrnInfoPtr pScrn)
{
- vgaHWPtr hwp;
NVPtr pNv;
NVRamdacPtr NVdac;
xf86MonPtr MonInfo = NULL;
- hwp = VGAHWPTR(pScrn);
pNv = NVPTR(pScrn);
NVdac = &pNv->Dac;
@@ -800,7 +790,6 @@
/* if ((MonInfo = nvDoDDCVBE(pScrn))) return MonInfo; */
/* Enable access to extended registers */
- vgaHWUnlock(hwp);
pNv->riva.LockUnlock(&pNv->riva, 0);
/* Save the current state */
NVSave(pScrn);
@@ -814,7 +803,6 @@
/* Restore previous state */
NVRestore(pScrn);
pNv->riva.LockUnlock(&pNv->riva, 1);
- vgaHWLock(hwp);
return MonInfo;
}
@@ -1141,10 +1129,22 @@
(((pScrn->mask.blue >> pScrn->offset.blue) - 1) << pScrn->offset.blue);
}
+ /* Doesn't work */
if (xf86ReturnOptValBool(pNv->Options, OPTION_FLAT_PANEL, FALSE)) {
pNv->FlatPanel = TRUE;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "using flat panel\n");
}
+
+ if (xf86GetOptValInteger(pNv->Options, OPTION_CRTC_NUMBER,
+ &pNv->forceCRTC))
+ {
+ if((pNv->forceCRTC < 0) || (pNv->forceCRTC > 1)) {
+ pNv->forceCRTC = -1;
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
+ "Invalid CRTC number. Must be 0 or 1\n");
+ }
+ } else pNv->forceCRTC = -1;
+
if (pNv->pEnt->device->MemBase != 0) {
/* Require that the config file value matches one of the PCI values. */
@@ -1318,6 +1318,7 @@
case NV_ARCH_04:
case NV_ARCH_10:
case NV_ARCH_20:
+ default:
pNv->FbUsableSize -= 128 * 1024;
break;
}
@@ -1344,6 +1345,11 @@
clockRanges->interlaceAllowed = FALSE;
clockRanges->doubleScanAllowed = TRUE;
+ if(pNv->FlatPanel) {
+ clockRanges->interlaceAllowed = FALSE;
+ clockRanges->doubleScanAllowed = FALSE;
+ }
+
/*
* xf86ValidateModes will check that the mode HTotal and VTotal values
* don't exceed the chipset's limit if pScrn->maxHValue and
@@ -1538,9 +1544,7 @@
/*
- * Initialise a new mode. This is currently still using the old
- * "initialise struct, restore/write struct to HW" model. That could
- * be changed.
+ * Initialise a new mode.
*/
static Bool
@@ -1558,18 +1562,15 @@
return FALSE;
pScrn->vtSema = TRUE;
- if ( pNv->ModeInit ) {
- if (!(*pNv->ModeInit)(pScrn, mode))
- return FALSE;
- }
+ if(!(*pNv->ModeInit)(pScrn, mode))
+ return FALSE;
/* Program the registers */
vgaHWProtect(pScrn, TRUE);
vgaReg = &hwp->ModeReg;
nvReg = &pNv->ModeReg;
- if ( pNv->Restore )
- (*pNv->Restore)(pScrn, vgaReg, nvReg, FALSE);
+ (*pNv->Restore)(pScrn, vgaReg, nvReg, FALSE);
#if X_BYTE_ORDER == X_BIG_ENDIAN
/* turn on LFB swapping */
@@ -1606,10 +1607,7 @@
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NVRestore\n"));
/* Only restore text mode fonts/text for the primary card */
vgaHWProtect(pScrn, TRUE);
- if (pNv->Primary)
- (*pNv->Restore)(pScrn, vgaReg, nvReg, TRUE);
- else
- vgaHWRestore(pScrn, vgaReg, VGA_SR_MODE);
+ (*pNv->Restore)(pScrn, vgaReg, nvReg, pNv->Primary);
vgaHWProtect(pScrn, FALSE);
}
@@ -1666,7 +1664,6 @@
return FALSE;
} else {
/* Save the current state */
- vgaHWUnlock(hwp);
pNv->riva.LockUnlock(&pNv->riva, 0);
NVSave(pScrn);
/* Initialise the first mode */
@@ -1897,12 +1894,6 @@
vgaRegPtr vgaReg = &pVga->SavedReg;
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NVSave\n"));
-#if defined(__powerpc__)
- /* The console driver will have to save the fonts, we can't */
- vgaHWSave(pScrn, vgaReg, VGA_SR_CMAP | VGA_SR_MODE);
-#else
- vgaHWSave(pScrn, vgaReg, VGA_SR_CMAP | VGA_SR_MODE | VGA_SR_FONTS);
-#endif
- pNv->riva.UnloadStateExt(&pNv->riva, nvReg);
+ (*pNv->Save)(pScrn, vgaReg, nvReg, pNv->Primary);
}
diff -uNr nv.orig/nv_local.h nv/nv_local.h
--- nv.orig/nv_local.h Mon Feb 25 22:54:49 2002
+++ nv/nv_local.h Mon Feb 25 22:54:45 2002
@@ -36,40 +36,39 @@
|* those rights set forth herein. *|
|* *|
\***************************************************************************/
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_local.h,v 1.6 2000/11/03
18:46:12 eich Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_local.h,v 1.7 2002/01/25
+21:56:06 tsi Exp $ */
#ifndef __NV_LOCAL_H__
#define __NV_LOCAL_H__
+
/*
- * This file includes any environment or machine specific values to access the HW.
- * Put all affected includes, typdefs, etc. here so the riva_hw.* files can stay
- * generic in nature.
+ * This file includes any environment or machine specific values to access the
+ * HW. Put all affected includes, typdefs, etc. here so the riva_hw.* files
+ * can stay generic in nature.
*/
#include "xf86_ansic.h"
#include "compiler.h"
+#include "xf86_OSproc.h"
+
/*
* Typedefs to force certain sized values.
*/
typedef unsigned char U008;
typedef unsigned short U016;
typedef unsigned int U032;
+
/*
- * HW access macros.
+ * HW access macros. These assume memory-mapped I/O, and not normal I/O space.
*/
-#include "xf86_OSproc.h"
-/* these assume memory-mapped I/O, and not normal I/O space */
#define NV_WR08(p,i,d) MMIO_OUT8((volatile pointer)(p), (i), (d))
#define NV_RD08(p,i) MMIO_IN8((volatile pointer)(p), (i))
#define NV_WR16(p,i,d) MMIO_OUT16((volatile pointer)(p), (i), (d))
#define NV_RD16(p,i) MMIO_IN16((volatile pointer)(p), (i))
#define NV_WR32(p,i,d) MMIO_OUT32((volatile pointer)(p), (i), (d))
#define NV_RD32(p,i) MMIO_IN32((volatile pointer)(p), (i))
-#if 1
+
+/* VGA I/O is now always done through MMIO */
#define VGA_WR08(p,i,d) NV_WR08(p,i,d)
#define VGA_RD08(p,i) NV_RD08(p,i)
-#else
-#define VGA_WR08(p,i,d) outb(i,d)
-#define VGA_RD08(p,i) inb(i)
-#endif
-#endif /* __NV_LOCAL_H__ */
+#endif /* __NV_LOCAL_H__ */
diff -uNr nv.orig/nv_setup.c nv/nv_setup.c
--- nv.orig/nv_setup.c Mon Feb 25 22:54:49 2002
+++ nv/nv_setup.c Mon Feb 25 22:55:47 2002
@@ -155,6 +155,69 @@
return (VGA_RD08(pNv->riva.PDIO, VGA_DAC_DATA));
}
+static Bool
+NVIsConnected (ScrnInfoPtr pScrn, Bool second)
+{
+ NVPtr pNv = NVPTR(pScrn);
+ volatile U032 *PRAMDAC = pNv->riva.PRAMDAC0;
+ CARD32 reg52C, reg608;
+ Bool present;
+
+ if(second) PRAMDAC += 0x800;
+
+ reg52C = PRAMDAC[0x052C/4];
+ reg608 = PRAMDAC[0x0608/4];
+
+ PRAMDAC[0x0608/4] = reg608 & ~0x00010000;
+
+ PRAMDAC[0x052C/4] = reg52C & 0x0000FEEE;
+ usleep(1000);
+ PRAMDAC[0x052C/4] |= 1;
+
+ pNv->riva.PRAMDAC0[0x0610/4] = 0x94050140;
+ pNv->riva.PRAMDAC0[0x0608/4] |= 0x00001000;
+
+ usleep(1000);
+
+ present = (PRAMDAC[0x0608/4] & (1 << 28)) ? TRUE : FALSE;
+
+ pNv->riva.PRAMDAC0[0x0608/4] &= 0x0000EFFF;
+
+ PRAMDAC[0x052C/4] = reg52C;
+ PRAMDAC[0x0608/4] = reg608;
+
+ return present;
+}
+
+static void
+NVIsSecond (ScrnInfoPtr pScrn)
+{
+ NVPtr pNv = NVPTR(pScrn);
+
+ if(NVIsConnected(pScrn, 0)) {
+ if(pNv->riva.PRAMDAC0[0x0000052C/4] & 0x100)
+ pNv->SecondCRTC = TRUE;
+ else
+ pNv->SecondCRTC = FALSE;
+ } else
+ if (NVIsConnected(pScrn, 1)) {
+ if(pNv->riva.PRAMDAC0[0x0000252C/4] & 0x100)
+ pNv->SecondCRTC = TRUE;
+ else
+ pNv->SecondCRTC = FALSE;
+ } else /* default */
+ pNv->SecondCRTC = FALSE;
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Detected CRTC controller %i being used\n",
+ pNv->SecondCRTC ? 1 : 0);
+
+ if(pNv->forceCRTC != -1) {
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
+ "Forcing usage of CRTC %i\n", pNv->forceCRTC);
+ pNv->SecondCRTC = pNv->forceCRTC;
+ }
+}
static void
NVCommonSetup(ScrnInfoPtr pScrn)
@@ -216,9 +279,9 @@
mmioFlags = VIDMEM_MMIO | VIDMEM_READSIDEEFFECT;
- pNv->riva.PRAMDAC = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
+ pNv->riva.PRAMDAC0 = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
regBase+0x00680000, 0x00003000);
- DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "- PRAMDAC %x\n", pNv->riva.PRAMDAC));
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "- PRAMDAC %x\n",
+pNv->riva.PRAMDAC0));
pNv->riva.PFB = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
regBase+0x00100000, 0x00001000);
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "- PFB %x\n", pNv->riva.PFB));
@@ -245,21 +308,50 @@
* These registers are read/write as 8 bit values. Probably have to map
* sparse on alpha.
*/
- pNv->riva.PCIO = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
+ pNv->riva.PCIO0 = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
pNv->PciTag, regBase+0x00601000,
- 0x00001000);
- pNv->riva.PDIO = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
+ 0x00003000);
+ pNv->riva.PDIO0 = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
pNv->PciTag, regBase+0x00681000,
- 0x00001000);
+ 0x00003000);
pNv->riva.PVIO = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
pNv->PciTag, regBase+0x000C0000,
0x00001000);
-
+
+ switch(pNv->Chipset & 0x0ff0) {
+ case 0x0110:
+ if((pNv->Chipset & 0x0fff) == 0x0112)
+ pNv->SecondCRTC = TRUE;
+ break;
+ case 0x0170:
+ case 0x0250:
+ NVIsSecond(pScrn);
+ break;
+ default:
+ break;
+ }
+
+#if defined(__powerpc__)
+ if(pNv->FlatPanel)
+ pNv->SecondCRTC = TRUE;
+#endif
+
+ if(pNv->SecondCRTC) {
+ pNv->riva.PCIO = pNv->riva.PCIO0 + 0x2000;
+ pNv->riva.PCRTC = pNv->riva.PCRTC0 + 0x800;
+ pNv->riva.PRAMDAC = pNv->riva.PRAMDAC0 + 0x800;
+ pNv->riva.PDIO = pNv->riva.PDIO0 + 0x2000;
+ } else {
+ pNv->riva.PCIO = pNv->riva.PCIO0;
+ pNv->riva.PCRTC = pNv->riva.PCRTC0;
+ pNv->riva.PRAMDAC = pNv->riva.PRAMDAC0;
+ pNv->riva.PDIO = pNv->riva.PDIO0;
+ }
+
RivaGetConfig(pNv);
pNv->Dac.maxPixelClock = pNv->riva.MaxVClockFreqKHz;
- vgaHWUnlock(VGAHWPTR(pScrn));
pNv->riva.LockUnlock(&pNv->riva, 0);
}
@@ -289,6 +381,7 @@
frameBase+0x00C00000, 0x00008000);
NVCommonSetup(pScrn);
+ pNv->riva.PCRTC = pNv->riva.PCRTC0 = pNv->riva.PGRAPH;
}
void
@@ -307,11 +400,12 @@
mmioFlags = VIDMEM_MMIO | VIDMEM_READSIDEEFFECT;
pNv->riva.PRAMIN = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
regBase+0x00710000, 0x00010000);
- pNv->riva.PCRTC = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
+ pNv->riva.PCRTC0 = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
regBase+0x00600000, 0x00001000);
NVCommonSetup(pScrn);
}
+
void
NV10Setup(ScrnInfoPtr pScrn)
{
@@ -322,14 +416,11 @@
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NV10Setup\n"));
pNv->riva.Architecture = 0x10;
- /*
- * Map chip-specific memory-mapped registers. This MUST be done in the OS
specific driver code.
- */
mmioFlags = VIDMEM_MMIO | VIDMEM_READSIDEEFFECT;
pNv->riva.PRAMIN = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
regBase+0x00710000, 0x00010000);
- pNv->riva.PCRTC = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
- regBase+0x00600000, 0x00001000);
+ pNv->riva.PCRTC0 = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
+ regBase+0x00600000, 0x00003000);
NVCommonSetup(pScrn);
}
@@ -341,18 +432,14 @@
CARD32 regBase = pNv->IOAddress;
int mmioFlags;
- DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NV10Setup\n"));
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NV20Setup\n"));
pNv->riva.Architecture = 0x20;
- /*
- * Map chip-specific memory-mapped registers. This MUST be done in the OS sp
-ecific driver code.
- */
mmioFlags = VIDMEM_MMIO | VIDMEM_READSIDEEFFECT;
pNv->riva.PRAMIN = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
regBase+0x00710000, 0x00010000);
- pNv->riva.PCRTC = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
- regBase+0x00600000, 0x00001000);
+ pNv->riva.PCRTC0 = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
+ regBase+0x00600000, 0x00003000);
NVCommonSetup(pScrn);
}
diff -uNr nv.orig/nv_type.h nv/nv_type.h
--- nv.orig/nv_type.h Mon Feb 25 22:54:49 2002
+++ nv/nv_type.h Mon Feb 25 22:54:45 2002
@@ -114,6 +114,8 @@
XF86VideoAdaptorPtr overlayAdaptor;
int videoKey;
Bool FlatPanel;
+ Bool SecondCRTC;
+ int forceCRTC;
OptionInfoPtr Options;
} NVRec, *NVPtr;
diff -uNr nv.orig/nvreg.h nv/nvreg.h
--- nv.orig/nvreg.h Mon Feb 25 22:54:49 2002
+++ nv/nvreg.h Mon Feb 25 22:54:45 2002
@@ -164,18 +164,9 @@
(PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\
(PDAC_Write(INDEX_DATA,(value))))
-#define CRTC_Write(index,value) outb(0x3d4,(index));outb(0x3d5,value)
-#define CRTC_Read(index) (outb(0x3d4,index),inb(0x3d5))
-
-#define PCRTC_Write(index,value) CRTC_Write(NV_PCRTC_##index,value)
-#define PCRTC_Read(index) CRTC_Read(NV_PCRTC_##index)
-
#define PCRTC_Def(mask,value) DEVICE_DEF(PCRTC,mask,value)
#define PCRTC_Val(mask,value) DEVICE_VALUE(PCRTC,mask,value)
#define PCRTC_Mask(mask) DEVICE_MASK(PCRTC,mask)
-
-#define SR_Write(index,value) outb(0x3c4,(index));outb(0x3c5,value)
-#define SR_Read(index) (outb(0x3c4,index),inb(0x3c5))
/* These are the variables which actually point at the register blocks */
diff -uNr nv.orig/riva_hw.c nv/riva_hw.c
--- nv.orig/riva_hw.c Mon Feb 25 22:54:49 2002
+++ nv/riva_hw.c Mon Feb 25 22:54:45 2002
@@ -70,34 +70,40 @@
{
return ((chip->Rop->FifoFree < chip->FifoEmptyCount) ||
(chip->PGRAPH[0x00000700/4] & 0x01));
}
-static void nv3LockUnlock
+static void vgaLockUnlock
(
RIVA_HW_INST *chip,
- int LockUnlock
+ Bool Lock
)
{
- VGA_WR08(chip->PVIO, 0x3C4, 0x06);
- VGA_WR08(chip->PVIO, 0x3C5, LockUnlock ? 0x99 : 0x57);
+ CARD8 cr11;
+ VGA_WR08(chip->PCIO, 0x3D4, 0x11);
+ cr11 = VGA_RD08(chip->PCIO, 0x3D5);
+ if(Lock) cr11 |= 0x80;
+ else cr11 &= ~0x80;
+ VGA_WR08(chip->PCIO, 0x3D5, cr11);
}
-static void nv4LockUnlock
+
+static void nv3LockUnlock
(
RIVA_HW_INST *chip,
- int LockUnlock
+ Bool Lock
)
{
- VGA_WR08(chip->PCIO, 0x3D4, 0x1F);
- VGA_WR08(chip->PCIO, 0x3D5, LockUnlock ? 0x99 : 0x57);
+ VGA_WR08(chip->PVIO, 0x3C4, 0x06);
+ VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57);
+ vgaLockUnlock(chip, Lock);
}
-static void nv10LockUnlock
+static void nv4LockUnlock
(
RIVA_HW_INST *chip,
- int LockUnlock
+ Bool Lock
)
{
VGA_WR08(chip->PCIO, 0x3D4, 0x1F);
- VGA_WR08(chip->PCIO, 0x3D5, LockUnlock ? 0x99 : 0x57);
+ VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57);
+ vgaLockUnlock(chip, Lock);
}
-
static int ShowHideCursor
(
RIVA_HW_INST *chip,
@@ -601,7 +607,7 @@
nv3_sim_state sim_data;
unsigned int M, N, P, pll, MClk;
- pll = chip->PRAMDAC[0x00000504/4];
+ pll = chip->PRAMDAC0[0x00000504/4];
M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
MClk = (N * chip->CrystalFreqKHz / M) >> P;
sim_data.pix_bpp = (char)pixelDepth;
@@ -788,10 +794,10 @@
nv4_sim_state sim_data;
unsigned int M, N, P, pll, MClk, NVClk, cfg1;
- pll = chip->PRAMDAC[0x00000504/4];
+ pll = chip->PRAMDAC0[0x00000504/4];
M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
MClk = (N * chip->CrystalFreqKHz / M) >> P;
- pll = chip->PRAMDAC[0x00000500/4];
+ pll = chip->PRAMDAC0[0x00000500/4];
M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
NVClk = (N * chip->CrystalFreqKHz / M) >> P;
cfg1 = chip->PFB[0x00000204/4];
@@ -1049,10 +1055,10 @@
nv10_sim_state sim_data;
unsigned int M, N, P, pll, MClk, NVClk, cfg1;
- pll = chip->PRAMDAC[0x00000504/4];
+ pll = chip->PRAMDAC0[0x00000504/4];
M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
MClk = (N * chip->CrystalFreqKHz / M) >> P;
- pll = chip->PRAMDAC[0x00000500/4];
+ pll = chip->PRAMDAC0[0x00000500/4];
M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
NVClk = (N * chip->CrystalFreqKHz / M) >> P;
cfg1 = chip->PFB[0x00000204/4];
@@ -1272,18 +1278,10 @@
{
case NV_ARCH_04:
LOAD_FIXED_STATE(nv4,FIFO);
- chip->Tri03 = 0L;
- chip->Tri05 = (RivaTexturedTriangle05 *)&(chip->FIFO[0x0000E000/4]);
break;
case NV_ARCH_10:
case NV_ARCH_20:
- /*
- * Initialize state for the RivaTriangle3D05 routines.
- */
- LOAD_FIXED_STATE(nv10tri05,PGRAPH);
LOAD_FIXED_STATE(nv10,FIFO);
- chip->Tri03 = 0L;
- chip->Tri05 = (RivaTexturedTriangle05 *)&(chip->FIFO[0x0000E000/4]);
break;
}
}
@@ -1316,19 +1314,16 @@
case 16:
LOAD_FIXED_STATE_15BPP(nv3,PRAMIN);
LOAD_FIXED_STATE_15BPP(nv3,PGRAPH);
- chip->Tri03 = (RivaTexturedTriangle03
*)&(chip->FIFO[0x0000E000/4]);
break;
case 24:
case 32:
LOAD_FIXED_STATE_32BPP(nv3,PRAMIN);
LOAD_FIXED_STATE_32BPP(nv3,PGRAPH);
- chip->Tri03 = 0L;
break;
case 8:
default:
LOAD_FIXED_STATE_8BPP(nv3,PRAMIN);
LOAD_FIXED_STATE_8BPP(nv3,PGRAPH);
- chip->Tri03 = 0L;
break;
}
for (i = 0x00000; i < 0x00800; i++)
@@ -1355,24 +1350,20 @@
case 15:
LOAD_FIXED_STATE_15BPP(nv4,PRAMIN);
LOAD_FIXED_STATE_15BPP(nv4,PGRAPH);
- chip->Tri03 = (RivaTexturedTriangle03
*)&(chip->FIFO[0x0000E000/4]);
break;
case 16:
LOAD_FIXED_STATE_16BPP(nv4,PRAMIN);
LOAD_FIXED_STATE_16BPP(nv4,PGRAPH);
- chip->Tri03 = (RivaTexturedTriangle03
*)&(chip->FIFO[0x0000E000/4]);
break;
case 24:
case 32:
LOAD_FIXED_STATE_32BPP(nv4,PRAMIN);
LOAD_FIXED_STATE_32BPP(nv4,PGRAPH);
- chip->Tri03 = 0L;
break;
case 8:
default:
LOAD_FIXED_STATE_8BPP(nv4,PRAMIN);
LOAD_FIXED_STATE_8BPP(nv4,PGRAPH);
- chip->Tri03 = 0L;
break;
}
chip->PGRAPH[0x00000640/4] = state->offset0;
@@ -1386,6 +1377,12 @@
break;
case NV_ARCH_10:
case NV_ARCH_20:
+ if(chip->twoHeads) {
+ VGA_WR08(chip->PCIO, 0x03D4, 0x44);
+ VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner);
+ chip->LockUnlock(chip, 0);
+ }
+
LOAD_FIXED_STATE(nv10,PFIFO);
LOAD_FIXED_STATE(nv10,PRAMIN);
LOAD_FIXED_STATE(nv10,PGRAPH);
@@ -1394,24 +1391,20 @@
case 15:
LOAD_FIXED_STATE_15BPP(nv10,PRAMIN);
LOAD_FIXED_STATE_15BPP(nv10,PGRAPH);
- chip->Tri03 = (RivaTexturedTriangle03
*)&(chip->FIFO[0x0000E000/4]);
break;
case 16:
LOAD_FIXED_STATE_16BPP(nv10,PRAMIN);
LOAD_FIXED_STATE_16BPP(nv10,PGRAPH);
- chip->Tri03 = (RivaTexturedTriangle03
*)&(chip->FIFO[0x0000E000/4]);
break;
case 24:
case 32:
LOAD_FIXED_STATE_32BPP(nv10,PRAMIN);
LOAD_FIXED_STATE_32BPP(nv10,PGRAPH);
- chip->Tri03 = 0L;
break;
case 8:
default:
LOAD_FIXED_STATE_8BPP(nv10,PRAMIN);
LOAD_FIXED_STATE_8BPP(nv10,PGRAPH);
- chip->Tri03 = 0L;
break;
}
@@ -1438,11 +1431,12 @@
chip->PGRAPH[0x00000864/4] = state->pitch3;
chip->PGRAPH[0x000009A4/4] = chip->PFB[0x00000200/4];
chip->PGRAPH[0x000009A8/4] = chip->PFB[0x00000204/4];
- chip->PRAMDAC[0x0000052C/4] = 0x00000101;
- chip->PRAMDAC[0x0000252C/4] = 0x00000001;
}
+ if(chip->twoHeads) {
+ chip->PCRTC0[0x00000860/4] = state->head;
+ chip->PCRTC0[0x00002860/4] = state->head2;
+ }
chip->PRAMDAC[0x00000404/4] |= (1 << 25);
- chip->PRAMDAC[0x00002404/4] |= (1 << 25);
chip->PMC[0x00008704/4] = 1;
chip->PMC[0x00008140/4] = 0;
@@ -1450,6 +1444,7 @@
chip->PMC[0x00008924/4] = 0;
chip->PMC[0x00008908/4] = 0x01ffffff;
chip->PMC[0x0000890C/4] = 0x01ffffff;
+ chip->PMC[0x00001588/4] = 0;
chip->PFB[0x00000240/4] = 0;
chip->PFB[0x00000244/4] = 0;
@@ -1533,14 +1528,24 @@
chip->PGRAPH[0x00000F50/4] = 0x00000040;
for (i = 0; i < 4; i++)
chip->PGRAPH[0x00000F54/4] = 0x00000000;
+
+ if(chip->flatPanel) {
+ VGA_WR08(chip->PCIO, 0x03D4, 0x53);
+ VGA_WR08(chip->PCIO, 0x03D5, 0);
+ VGA_WR08(chip->PCIO, 0x03D4, 0x54);
+ VGA_WR08(chip->PCIO, 0x03D5, 0);
+ VGA_WR08(chip->PCIO, 0x03D4, 0x21);
+ VGA_WR08(chip->PCIO, 0x03D5, 0xfa);
+ }
break;
}
+
LOAD_FIXED_STATE(Riva,FIFO);
UpdateFifoState(chip);
+
/*
* Load HW mode state.
*/
-
VGA_WR08(chip->PCIO, 0x03D4, 0x19);
VGA_WR08(chip->PCIO, 0x03D5, state->repaint0);
VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
@@ -1565,14 +1570,21 @@
VGA_WR08(chip->PCIO, 0x03D5, state->interlace);
VGA_WR08(chip->PCIO, 0x03D4, 0x41);
VGA_WR08(chip->PCIO, 0x03D5, state->extra);
- chip->PRAMDAC[0x00000508/4] = state->vpll;
- chip->PRAMDAC[0x0000050C/4] = state->pllsel;
+
+ if(!chip->flatPanel) {
+ chip->PRAMDAC0[0x00000508/4] = state->vpll;
+ chip->PRAMDAC0[0x00000520/4] = state->vpll2;
+ chip->PRAMDAC0[0x0000050C/4] = state->pllsel;
+ } else {
+ chip->PRAMDAC[0x00000848/4] = state->scale;
+ }
chip->PRAMDAC[0x00000600/4] = state->general;
+
/*
* Turn off VBlank enable and reset.
*/
- *(chip->VBLANKENABLE) = 0;
- *(chip->VBLANK) = chip->VBlankBit;
+ chip->PCRTC[0x00000140/4] = 0;
+ chip->PCRTC[0x00000100/4] = chip->VBlankBit;
/*
* Set interrupt enable.
*/
@@ -1588,6 +1600,7 @@
/* Free count from first subchannel */
chip->FifoEmptyCount = chip->Rop->FifoFree;
}
+
static void UnloadStateExt
(
RIVA_HW_INST *chip,
@@ -1621,10 +1634,13 @@
state->interlace = VGA_RD08(chip->PCIO, 0x03D5);
VGA_WR08(chip->PCIO, 0x03D4, 0x41);
state->extra = VGA_RD08(chip->PCIO, 0x03D5);
- state->vpll = chip->PRAMDAC[0x00000508/4];
- state->pllsel = chip->PRAMDAC[0x0000050C/4];
+ state->vpll = chip->PRAMDAC0[0x00000508/4];
+ state->vpll2 = chip->PRAMDAC0[0x00000520/4];
+ state->pllsel = chip->PRAMDAC0[0x0000050C/4];
state->general = chip->PRAMDAC[0x00000600/4];
+ state->scale = chip->PRAMDAC[0x00000848/4];
state->config = chip->PFB[0x00000200/4];
+
switch (chip->Architecture)
{
case NV_ARCH_03:
@@ -1657,6 +1673,13 @@
state->pitch1 = chip->PGRAPH[0x00000674/4];
state->pitch2 = chip->PGRAPH[0x00000678/4];
state->pitch3 = chip->PGRAPH[0x0000067C/4];
+ if(chip->twoHeads) {
+ state->head = chip->PCRTC0[0x00000860/4];
+ state->head2 = chip->PCRTC0[0x00002860/4];
+ VGA_WR08(chip->PCIO, 0x03D4, 0x44);
+ state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5);
+ }
+
break;
}
}
@@ -1666,6 +1689,15 @@
unsigned start
)
{
+ chip->PCRTC[0x800/4] = start;
+}
+
+static void SetStartAddress3
+(
+ RIVA_HW_INST *chip,
+ unsigned start
+)
+{
int offset = start >> 2;
int pan = (start & 3) << 1;
unsigned char tmp;
@@ -1692,99 +1724,6 @@
VGA_WR08(chip->PCIO, 0x3C0, 0x13);
VGA_WR08(chip->PCIO, 0x3C0, pan);
}
-static void nv3SetSurfaces2D
-(
- RIVA_HW_INST *chip,
- unsigned surf0,
- unsigned surf1
-)
-{
- RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]);
-
- RIVA_FIFO_FREE(*chip,Tri03,5);
- chip->FIFO[0x00003800] = 0x80000003;
- Surface->Offset = surf0;
- chip->FIFO[0x00003800] = 0x80000004;
- Surface->Offset = surf1;
- chip->FIFO[0x00003800] = 0x80000013;
-}
-static void nv4SetSurfaces2D
-(
- RIVA_HW_INST *chip,
- unsigned surf0,
- unsigned surf1
-)
-{
- RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]);
-
- chip->FIFO[0x00003800] = 0x80000003;
- Surface->Offset = surf0;
- chip->FIFO[0x00003800] = 0x80000004;
- Surface->Offset = surf1;
- chip->FIFO[0x00003800] = 0x80000014;
-}
-static void nv10SetSurfaces2D
-(
- RIVA_HW_INST *chip,
- unsigned surf0,
- unsigned surf1
-)
-{
- RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]);
-
- chip->FIFO[0x00003800] = 0x80000003;
- Surface->Offset = surf0;
- chip->FIFO[0x00003800] = 0x80000004;
- Surface->Offset = surf1;
- chip->FIFO[0x00003800] = 0x80000014;
-}
-static void nv3SetSurfaces3D
-(
- RIVA_HW_INST *chip,
- unsigned surf0,
- unsigned surf1
-)
-{
- RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]);
-
- RIVA_FIFO_FREE(*chip,Tri03,5);
- chip->FIFO[0x00003800] = 0x80000005;
- Surface->Offset = surf0;
- chip->FIFO[0x00003800] = 0x80000006;
- Surface->Offset = surf1;
- chip->FIFO[0x00003800] = 0x80000013;
-}
-static void nv4SetSurfaces3D
-(
- RIVA_HW_INST *chip,
- unsigned surf0,
- unsigned surf1
-)
-{
- RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]);
-
- chip->FIFO[0x00003800] = 0x80000005;
- Surface->Offset = surf0;
- chip->FIFO[0x00003800] = 0x80000006;
- Surface->Offset = surf1;
- chip->FIFO[0x00003800] = 0x80000014;
-}
-static void nv10SetSurfaces3D
-(
- RIVA_HW_INST *chip,
- unsigned surf0,
- unsigned surf1
-)
-{
- RivaSurface3D *Surfaces3D = (RivaSurface3D *)&(chip->FIFO[0x0000E000/4]);
-
- RIVA_FIFO_FREE(*chip,Tri03,4);
- chip->FIFO[0x00003800] = 0x80000007;
- Surfaces3D->RenderBufferOffset = surf0;
- Surfaces3D->ZBufferOffset = surf1;
- chip->FIFO[0x00003800] = 0x80000014;
-}
-
/****************************************************************************\
* *
* Probe RIVA Chip Configuration *
@@ -1848,9 +1787,6 @@
}
chip->CrystalFreqKHz = (chip->PEXTDEV[0x00000000/4] & 0x00000040) ? 14318 :
13500;
chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]);
- chip->CURSORPOS = &(chip->PRAMDAC[0x0300/4]);
- chip->VBLANKENABLE = &(chip->PGRAPH[0x0140/4]);
- chip->VBLANK = &(chip->PGRAPH[0x0100/4]);
chip->VBlankBit = 0x00000100;
chip->MaxVClockFreqKHz = 256000;
/*
@@ -1861,9 +1797,7 @@
chip->CalcStateExt = CalcStateExt;
chip->LoadStateExt = LoadStateExt;
chip->UnloadStateExt = UnloadStateExt;
- chip->SetStartAddress = SetStartAddress;
- chip->SetSurfaces2D = nv3SetSurfaces2D;
- chip->SetSurfaces3D = nv3SetSurfaces3D;
+ chip->SetStartAddress = SetStartAddress3;
chip->LockUnlock = nv3LockUnlock;
}
static void nv4GetConfig
@@ -1909,9 +1843,6 @@
}
chip->CrystalFreqKHz = (chip->PEXTDEV[0x00000000/4] & 0x00000040) ? 14318 :
13500;
chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]);
- chip->CURSORPOS = &(chip->PRAMDAC[0x0300/4]);
- chip->VBLANKENABLE = &(chip->PCRTC[0x0140/4]);
- chip->VBLANK = &(chip->PCRTC[0x0100/4]);
chip->VBlankBit = 0x00000001;
chip->MaxVClockFreqKHz = 350000;
/*
@@ -1923,8 +1854,6 @@
chip->LoadStateExt = LoadStateExt;
chip->UnloadStateExt = UnloadStateExt;
chip->SetStartAddress = SetStartAddress;
- chip->SetSurfaces2D = nv4SetSurfaces2D;
- chip->SetSurfaces3D = nv4SetSurfaces3D;
chip->LockUnlock = nv4LockUnlock;
}
static void nv10GetConfig
@@ -1989,9 +1918,6 @@
13500;
chip->CursorStart = (chip->RamAmountKBytes - 128) * 1024;
chip->CURSOR = NULL; /* can't set this here */
- chip->CURSORPOS = &(chip->PRAMDAC[0x0300/4]);
- chip->VBLANKENABLE = &(chip->PCRTC[0x0140/4]);
- chip->VBLANK = &(chip->PCRTC[0x0100/4]);
chip->VBlankBit = 0x00000001;
chip->MaxVClockFreqKHz = 350000;
/*
@@ -2003,9 +1929,18 @@
chip->LoadStateExt = LoadStateExt;
chip->UnloadStateExt = UnloadStateExt;
chip->SetStartAddress = SetStartAddress;
- chip->SetSurfaces2D = nv10SetSurfaces2D;
- chip->SetSurfaces3D = nv10SetSurfaces3D;
- chip->LockUnlock = nv10LockUnlock;
+ chip->LockUnlock = nv4LockUnlock;
+
+ switch(pNv->Chipset & 0x0ff0) {
+ case 0x0110:
+ case 0x0170:
+ case 0x0250:
+ chip->twoHeads = TRUE;
+ break;
+ default:
+ chip->twoHeads = FALSE;
+ break;
+ }
}
int RivaGetConfig
(
@@ -2035,6 +1970,7 @@
default:
return (-1);
}
+ chip->flatPanel = pNv->FlatPanel;
/*
* Fill in FIFO pointers.
*/
@@ -2045,7 +1981,6 @@
chip->Blt = (RivaScreenBlt *)&(chip->FIFO[0x00008000/4]);
chip->Bitmap = (RivaBitmap *)&(chip->FIFO[0x0000A000/4]);
chip->Line = (RivaLine *)&(chip->FIFO[0x0000C000/4]);
- chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]);
return (0);
}
diff -uNr nv.orig/riva_hw.h nv/riva_hw.h
--- nv.orig/riva_hw.h Mon Feb 25 22:54:49 2002
+++ nv/riva_hw.h Mon Feb 25 22:54:45 2002
@@ -225,74 +225,6 @@
U032 MonochromeData01E;
} RivaBitmap;
/*
- * 3D textured, Z buffered triangle.
- */
-typedef volatile struct
-{
- U032 reserved00[4];
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- U032 FifoFree;
-#else
- U016 FifoFree;
- U016 Nop;
-#endif
- U032 reserved01[0x0BC];
- U032 TextureOffset;
- U032 TextureFormat;
- U032 TextureFilter;
- U032 FogColor;
-/* This is a problem on LynxOS */
-#ifdef Control
-#undef Control
-#endif
- U032 Control;
- U032 AlphaTest;
- U032 reserved02[0x339];
- U032 FogAndIndex;
- U032 Color;
- float ScreenX;
- float ScreenY;
- float ScreenZ;
- float EyeM;
- float TextureS;
- float TextureT;
-} RivaTexturedTriangle03;
-typedef volatile struct
-{
- U032 reserved00[4];
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- U032 FifoFree;
-#else
- U016 FifoFree;
- U016 Nop;
-#endif
- U032 reserved01[0x0BB];
- U032 ColorKey;
- U032 TextureOffset;
- U032 TextureFormat;
- U032 TextureFilter;
- U032 Blend;
-/* This is a problem on LynxOS */
-#ifdef Control
-#undef Control
-#endif
- U032 Control;
- U032 FogColor;
- U032 reserved02[0x39];
- struct
- {
- float ScreenX;
- float ScreenY;
- float ScreenZ;
- float EyeM;
- U032 Color;
- U032 Specular;
- float TextureS;
- float TextureT;
- } Vertex[16];
- U032 DrawTriangle3D;
-} RivaTexturedTriangle05;
-/*
* 2D line.
*/
typedef volatile struct
@@ -385,11 +317,14 @@
U032 FifoFreeCount;
U032 FifoEmptyCount;
U032 CursorStart;
+ Bool flatPanel;
+ Bool twoHeads;
/*
* Non-FIFO registers.
*/
+ volatile U032 *PCRTC0;
volatile U032 *PCRTC;
- volatile U032 *PRAMDAC;
+ volatile U032 *PRAMDAC0;
volatile U032 *PFB;
volatile U032 *PFIFO;
volatile U032 *PGRAPH;
@@ -399,12 +334,12 @@
volatile U032 *PRAMIN;
volatile U032 *FIFO;
volatile U032 *CURSOR;
- volatile U032 *CURSORPOS;
- volatile U032 *VBLANKENABLE;
- volatile U032 *VBLANK;
+ volatile U008 *PCIO0;
volatile U008 *PCIO;
volatile U008 *PVIO;
+ volatile U008 *PDIO0;
volatile U008 *PDIO;
+ volatile U032 *PRAMDAC;
/*
* Common chip functions.
*/
@@ -413,8 +348,6 @@
void (*LoadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
void (*UnloadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
void (*SetStartAddress)(struct _riva_hw_inst *,U032);
- void (*SetSurfaces2D)(struct _riva_hw_inst *,U032,U032);
- void (*SetSurfaces3D)(struct _riva_hw_inst *,U032,U032);
int (*ShowHideCursor)(struct _riva_hw_inst *,int);
void (*LockUnlock)(struct _riva_hw_inst *, int);
/*
@@ -431,8 +364,6 @@
RivaScreenBlt *Blt;
RivaBitmap *Bitmap;
RivaLine *Line;
- RivaTexturedTriangle03 *Tri03;
- RivaTexturedTriangle05 *Tri05;
} RIVA_HW_INST;
/*
* Extended mode state information.
@@ -446,14 +377,19 @@
U032 repaint0;
U032 repaint1;
U032 screen;
+ U032 scale;
U032 extra;
U032 pixel;
U032 horiz;
U032 arbitration0;
U032 arbitration1;
U032 vpll;
+ U032 vpll2;
U032 pllsel;
U032 general;
+ U032 crtcOwner;
+ U032 head;
+ U032 head2;
U032 config;
U032 cursor0;
U032 cursor1;
diff -uNr nv.orig/riva_tbl.h nv/riva_tbl.h
--- nv.orig/riva_tbl.h Mon Feb 25 22:54:49 2002
+++ nv/riva_tbl.h Mon Feb 25 22:54:45 2002
@@ -633,180 +633,6 @@
{0x000001C9, 0x0077D777},
{0x00000186, 0x000070E5},
{0x0000020C, 0x0E0D0D0D}
-};
-static unsigned nv10tri05TablePGRAPH[][2] =
-{
- {(0x00000E00/4), 0x00000000},
- {(0x00000E04/4), 0x00000000},
- {(0x00000E08/4), 0x00000000},
- {(0x00000E0C/4), 0x00000000},
- {(0x00000E10/4), 0x00001000},
- {(0x00000E14/4), 0x00001000},
- {(0x00000E18/4), 0x4003ff80},
- {(0x00000E1C/4), 0x00000000},
- {(0x00000E20/4), 0x00000000},
- {(0x00000E24/4), 0x00000000},
- {(0x00000E28/4), 0x00000000},
- {(0x00000E2C/4), 0x00000000},
- {(0x00000E30/4), 0x00080008},
- {(0x00000E34/4), 0x00080008},
- {(0x00000E38/4), 0x00000000},
- {(0x00000E3C/4), 0x00000000},
- {(0x00000E40/4), 0x00000000},
- {(0x00000E44/4), 0x00000000},
- {(0x00000E48/4), 0x00000000},
- {(0x00000E4C/4), 0x00000000},
- {(0x00000E50/4), 0x00000000},
- {(0x00000E54/4), 0x00000000},
- {(0x00000E58/4), 0x00000000},
- {(0x00000E5C/4), 0x00000000},
- {(0x00000E60/4), 0x00000000},
- {(0x00000E64/4), 0x10000000},
- {(0x00000E68/4), 0x00000000},
- {(0x00000E6C/4), 0x00000000},
- {(0x00000E70/4), 0x00000000},
- {(0x00000E74/4), 0x00000000},
- {(0x00000E78/4), 0x00000000},
- {(0x00000E7C/4), 0x00000000},
- {(0x00000E80/4), 0x00000000},
- {(0x00000E84/4), 0x00000000},
- {(0x00000E88/4), 0x08000000},
- {(0x00000E8C/4), 0x00000000},
- {(0x00000E90/4), 0x00000000},
- {(0x00000E94/4), 0x00000000},
- {(0x00000E98/4), 0x00000000},
- {(0x00000E9C/4), 0x4B7FFFFF},
- {(0x00000EA0/4), 0x00000000},
- {(0x00000EA4/4), 0x00000000},
- {(0x00000EA8/4), 0x00000000},
- {(0x00000F00/4), 0x07FF0800},
- {(0x00000F04/4), 0x07FF0800},
- {(0x00000F08/4), 0x07FF0800},
- {(0x00000F0C/4), 0x07FF0800},
- {(0x00000F10/4), 0x07FF0800},
- {(0x00000F14/4), 0x07FF0800},
- {(0x00000F18/4), 0x07FF0800},
- {(0x00000F1C/4), 0x07FF0800},
- {(0x00000F20/4), 0x07FF0800},
- {(0x00000F24/4), 0x07FF0800},
- {(0x00000F28/4), 0x07FF0800},
- {(0x00000F2C/4), 0x07FF0800},
- {(0x00000F30/4), 0x07FF0800},
- {(0x00000F34/4), 0x07FF0800},
- {(0x00000F38/4), 0x07FF0800},
- {(0x00000F3C/4), 0x07FF0800},
- {(0x00000F40/4), 0x10000000},
- {(0x00000F44/4), 0x00000000},
- {(0x00000F50/4), 0x00006740},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F54/4), 0x3F800000},
- {(0x00000F50/4), 0x00006750},
- {(0x00000F54/4), 0x40000000},
- {(0x00000F54/4), 0x40000000},
- {(0x00000F54/4), 0x40000000},
- {(0x00000F54/4), 0x40000000},
- {(0x00000F50/4), 0x00006760},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F54/4), 0x3F800000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F50/4), 0x00006770},
- {(0x00000F54/4), 0xC5000000},
- {(0x00000F54/4), 0xC5000000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F50/4), 0x00006780},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F54/4), 0x3F800000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F50/4), 0x000067A0},
- {(0x00000F54/4), 0x3F800000},
- {(0x00000F54/4), 0x3F800000},
- {(0x00000F54/4), 0x3F800000},
- {(0x00000F54/4), 0x3F800000},
- {(0x00000F50/4), 0x00006AB0},
- {(0x00000F54/4), 0x3F800000},
- {(0x00000F54/4), 0x3F800000},
- {(0x00000F54/4), 0x3F800000},
- {(0x00000F50/4), 0x00006AC0},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F50/4), 0x00006C10},
- {(0x00000F54/4), 0xBF800000},
- {(0x00000F50/4), 0x00007030},
- {(0x00000F54/4), 0x7149F2CA},
- {(0x00000F50/4), 0x00007040},
- {(0x00000F54/4), 0x7149F2CA},
- {(0x00000F50/4), 0x00007050},
- {(0x00000F54/4), 0x7149F2CA},
- {(0x00000F50/4), 0x00007060},
- {(0x00000F54/4), 0x7149F2CA},
- {(0x00000F50/4), 0x00007070},
- {(0x00000F54/4), 0x7149F2CA},
- {(0x00000F50/4), 0x00007080},
- {(0x00000F54/4), 0x7149F2CA},
- {(0x00000F50/4), 0x00007090},
- {(0x00000F54/4), 0x7149F2CA},
- {(0x00000F50/4), 0x000070A0},
- {(0x00000F54/4), 0x7149F2CA},
- {(0x00000F50/4), 0x00006A80},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F54/4), 0x3F800000},
- {(0x00000F50/4), 0x00006AA0},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F50/4), 0x00000040},
- {(0x00000F54/4), 0x00000005},
- {(0x00000F50/4), 0x00006400},
- {(0x00000F54/4), 0x3F800000},
- {(0x00000F54/4), 0x3F800000},
- {(0x00000F54/4), 0x4B7FFFFF},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F50/4), 0x00006410},
- {(0x00000F54/4), 0xC5000000},
- {(0x00000F54/4), 0xC5000000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F50/4), 0x00006420},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F50/4), 0x00006430},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F50/4), 0x000064C0},
- {(0x00000F54/4), 0x3F800000},
- {(0x00000F54/4), 0x3F800000},
- {(0x00000F54/4), 0x477FFFFF},
- {(0x00000F54/4), 0x3F800000},
- {(0x00000F50/4), 0x000064D0},
- {(0x00000F54/4), 0xC5000000},
- {(0x00000F54/4), 0xC5000000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F50/4), 0x000064E0},
- {(0x00000F54/4), 0xC4FFF000},
- {(0x00000F54/4), 0xC4FFF000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F50/4), 0x000064F0},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F54/4), 0x00000000},
- {(0x00000F40/4), 0x30000000},
- {(0x00000F44/4), 0x00000004},
- {(0x00000F48/4), 0x10000000},
- {(0x00000F4C/4), 0x00000000}
};
static unsigned nv10TablePRAMIN[][2] =
{
