Although it hasn't been officially announced yet, the new version of
the cell was the subject of a presentation by IBM at the Cool Chips X
meeting in Japan. It is about what one would expect - they fixed the
things needing fixing and left the rest pretty much untouched. Thus,
the DP floating performance was vastly improved, IEEE FP conformance
was enhanced and the memory capacity was increased to 16 Gb (using
DDR2 but maintaining the 25 GB/s bandwidth). Claimed DP performance
is 102 GFLOPS max. The chip is 65 nm and dissipates 100 W at 3.2 GHz
(a slight improvement) and is slightly more complicated. Some more
details at:
http://www.ps3coderz.com/
Warren Nagourney
On Mar 20, 2007, at 7:53 AM, Jonathan Bartlett wrote:
Here's the next one in the series. Here, we switch from assembly
language to C/C++.
http://www-128.ibm.com/developerworks/power/library/pa-linuxps3-5/
Jon
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