Urgent required *ASIC Design Engineer *(MUST-*USB, FPGA, RTL, VHDL, PCIe,
Verilog, Modelsim/VCS, Synplify, Xilinx, Altera*) at TX for Direct Client

Please send the resumes only on* s...@cy-tec.com*


Austin, Texas

3 to 12 Months

*Rate is $50/hr on C2C maxxxxxx*

*FPGA is must*

*ASIC DESIGN; Board Design; CAD; Debug; RTL; Verilog*

Assignment Title: Hardware Engineer -*FPGA design*

Resumes MUST HAVE the following per client:

·  *RTL level experience with USB protocol and verification of USBs is a

·  *PCIe protocol, RTL level* implementation and verification is a must.

Comments:  Must work onsite no exceptions. Starting w/3 months with
extension every three.

Project Description: Support development of Intel Product.

Daily Responsibilities:

Please indicate % of travel required: <5%

Necessary Skills (Must Have):
.5 -7 years plus solid *FPGA/ASIC design experience.*
.*RTL design preferably in Verilog, System Verilog required and some
experience with VHDL* desired.
.Experience with complete design flow on multiple *FPGAs/ASICs*: synthesis,
place and route, static timing analysis, lab debug.
.Solid *PCIe RTL design experience.*
.Experience writing *Verilog/VHDL* and C testbenches, strong Perl or other
scripting languages, Unix/Linux environment.
. Tool experiences: *Modelsim/VCS, Synplify, Xilinx, Altera.*

Additional Skills Desired (Nice to Have):
o Board bring-up & debug experience.
o CAD tools experience for schematics capture & layout.
o Should have hands on experience with high speed Scope & logic analyzer.
o X86 Architecture knowledge along with high speed bus interfaces such as

Years of Experience & Expertise Level: 5-7 years

Thanks and Regards

Syed Muzaffer Ali

CyberTec Inc

703 544 3910

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