Thanks Robert, I'm afraid this confirms my fears that it is frequency dependent and therefore a problem for wideband use. The comment about the ADC083000 is more encouraging though...
-Francois On Wed, Feb 2, 2011 at 8:52 PM, Robert F. Jarnot < robert.f.jar...@jpl.nasa.gov> wrote: > Dana, > > I am not sure if this is simply the clock getting into the data path. I > remember thinking of it more as the ADC characteristics 'falling to pieces' > subtly when clocked at its maximum rate. If memory serves me correctly, > lowering the sample rate of each ADC from 1 Gsps to 500 Msps improved the > behavior dramatically, implying that something non-linear was going on. As > for the interleaving spurs, I am pretty sure that when we minimized them at > HF, they became worse at LF. We ended up just optimizing at LF, and made > sure that we did not change the clock amplitude. We did not investigate how > things changed with temperature, but in a lab environment we did not have to > go back and periodically change the ADC matching. > > Regards, > > Robert > > > On 02/02/2011 10:20 AM, dana whitlow wrote: > >> If offsets change with clock level, is that not an indication of clock >> getting >> into the analog input? If so, it is probably a combination of a little >> bit on >> the ADC chip itself and some from the board layout, which in principle >> could be reduced (but what a pain to figure out just what to do!). >> >> Regarding interleaving spurs, what happens if one adjusts the interleaving >> for minimal spurs at HF? Do they then get worse at LF? >> >> Dana Whitlow >> Arecibo Observatory >> >> >> On 2/2/2011 1:32 PM, Robert F. Jarnot wrote: >> >>> Hong, Paul, Francois, >>> >>> We (at JPL) have spent a fair amount of time in the past >>> struggling with interleaving the e2v AT84AD001B (iADC/iBOB >>> combination). At the highest sample rates (Glenn Jones kurtosis >>> spectrometer for example) we find that matching with low frequency >>> signals as Hong described works very well. With high frequency >>> signals however the results are quite different, and less >>> encouraging. We find that matching ADC characteristics with low >>> frequency signals does not necessarily lead to good results with high >>> frequency signals. This is supported by some of the statements in the >>> ADC FAQs at the e2v web site. Furthermore, we have seen some other >>> unexpected behavior, such as offsets changing with the amplitude of >>> the ADC clock signal (even within the range specified by the data >>> sheet). At lower sample rates the AT84AD001B behaves much better, and >>> I suspect that is why there is now an AT84AD001C. >>> >>> Our experience with interleaving the ADC083000 at 3 Gsps has been >>> very good in comparison. >>> >>> Robert Jarnot >>> >>>> Message: 2 >>>> Date: Tue, 1 Feb 2011 22:41:14 -0800 >>>> From: Hong Chen<chen_1...@berkeley.edu> >>>> Subject: Re: [casper] new memo - external adjustment for Atmel/e2v >>>> interleaved ADC's >>>> To: Paul Demorest<pdemo...@nrao.edu> >>>> Cc: CASPER Lists<casper@lists.berkeley.edu> >>>> Message-ID: >>>> <aanlktikmbeppzl9jbghsdnucgfw+6tgn0dioh_29a...@mail.gmail.com<aanlktikmbeppzl9jbghsdnucgfw%2b6tgn0dioh_29a...@mail.gmail.com> >>>> > >>>> Content-Type: text/plain; charset="iso-8859-1" >>>> >>>> Hello Paul, >>>> >>>> According to the datasheet, the adjustment steps are really small: >>>> 0.25LSB >>>> for offset adjustment, 0.005dB for gain adjustment and 4ps for phase >>>> adjustment. This resolution is very fine for the data we were >>>> dealing with >>>> (~100MHz, 8 bits), so theoretically we should get close to a perfect >>>> result, >>>> which the achieved one cannot even compare with. >>>> The reason why we can't achieve the predicted result seems to be >>>> beyond the >>>> interleaving issue, and currently my best guess is the existence of >>>> harmonic >>>> frequencies. When I look at the raw data directly (from a single >>>> ADC, with >>>> ~10MHz input signal frequency) and compare it with the 8-bit >>>> simulated data >>>> generated by matlab, I can see very obvious difference, the actual >>>> curve is >>>> rougher for some reason(attached graphs). It appears to be very >>>> difficult to >>>> do the perfect interleaving adjustment or to calculate the gain/phase >>>> when >>>> the other interfering factors are strong. >>>> >>>> Thank you for your question. I'm sorry I don't really know what >>>> "features of >>>> the ADCs" are limiting the performance. >>>> >>>> Best, >>>> Hong >>>> >>>> >>>> On Sat, Jan 29, 2011 at 7:20 AM, Paul Demorest<pdemo...@nrao.edu> >>>> wrote: >>>> >>>> Hi Hong and Mark, >>>>> >>>>> Thanks for writing this memo! This topic is important for our pulsar >>>>> instruments. I was wondering if you know what the limiting factor >>>>> is in how >>>>> good the adjustment can be. For example, given the available >>>>> resolution of >>>>> the gain/phase adjustments there should be a 'theoretical best' >>>>> performance. >>>>> How close is your adjustment to achieving that? Are there any other >>>>> features of the ADCs that might limit the performance? >>>>> >>>>> -Paul >>>>> >>>>> >>>>> On Fri, 28 Jan 2011, Hong Chen wrote: >>>>> >>>>> Dear Casperites, >>>>> >>>>>> Mark and I have finished a memo on the external adjustment for >>>>>> Atmel/e2v >>>>>> interleaved ADC's and >>>>>> it is item 40< >>>>>> >>>>>> http://casper.berkeley.edu/wiki/images/7/7f/Atmel_iadc_external_adjust.pdf >>>>>> >>>>>> in >>>>>>> >>>>>> Casper wiki's memos section. >>>>>> >>>>>> This memo investigates the interleaving issue on the e2v 1Gsps iADC >>>>>> board >>>>>> and implements python code to adjust the iadc gain, offset and >>>>>> delay by >>>>>> adjusting the control registers through the software interface. The >>>>>> result >>>>>> shows it is able to reduce the interleaving error by about 60%~85%. >>>>>> Your >>>>>> questions and comments will be appreciated. >>>>>> >>>>>> Thanks, >>>>>> Hong Chen >>>>>> >>>>>> End of casper Digest, Vol 39, Issue 2 >>>> ************************************* >>>> >>> >> > -- > * Robert F. Jarnot, M/S 183-701 | robert.f.jar...@jpl.nasa.gov * > * Jet Propulsion Laboratory, | Office: (818) 354-5204 * > * 4800 Oak Grove Drive, | Cell: (818) 653-9266 * > * Pasadena, CA 91109-8099, USA | FAX: (818) 393 5065 * > > >
