Hello all, I've been trying to move away from such big heavy models, my ultimate goal being to have VHDL black boxes instead of precompiled ones made from Xilinx or Casper DSP blocks.
Jack Hickish's HDL Black Box Tutorial ( https://casper.berkeley.edu/wiki/Tutorial_HDL_Black_Box) demonstrates a very simple example of this, but I wanted something which could be a little bit more dynamic, e.g. in terms of bit-widths for a given input. I started with a simple D-flip-flop block, which would automatically size itself according to what was put in at the input. Eventually I got it right. This is my VHDL code (important points noted with #### - these aren't obvious from the above tutorial): ################################################################################# library IEEE; use IEEE.std_logic_1164.all; entity d_flip_flop_nbit is generic (n_bits: positive); ##### port (D : in std_logic_vector(n_bits - 1 downto 0); #### clk, ce: in std_logic; Q : out std_logic_vector(n_bits - 1 downto 0)); #### end d_flip_flop_nbit; architecture behav of d_flip_flop_nbit is begin dffn: process (clk) begin if (rising_edge(clk)) then Q <= D; end if; end process dffn; end behav; ################################################################################# This is the accompanying config M-file: %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% function d_flip_flop_nbit_config(this_block) this_block.setTopLevelLanguage('VHDL'); this_block.setEntityName('d_flip_flop_nbit'); this_block.addSimulinkInport('D'); this_block.addSimulinkOutport('Q'); % ----------------------------- if (this_block.inputTypesKnown) this_block.addGeneric('n_bits','positive',num2str(this_block.port('D').width)); %%%%% %Sysgen user guide specifies these lines of code but Matlab doesn't like them. Apparently %the functions referred don't actually exist. What I have below is a bit of a hack but it worked. % q_port = this_block.port('Q'); % q_port.setWidth = this_block.port('D').width; % q_port.setBinPt(0); % q_port.makeUnsigned(); q_port = this_block.port('Q'); q_port_string = strcat('Ufix_',num2str(this_block.port('D').width),'_0'); %%%%% q_port.setType(q_port_string); end % if(inputTypesKnown) % ----------------------------- % ----------------------------- if (this_block.inputRatesKnown) setup_as_single_rate(this_block,'clk','ce') end % if(inputRatesKnown) % ----------------------------- uniqueInputRates = unique(this_block.getInputRates); this_block.addFile('d_flip_flop_nbit.vhd'); return; % ------------------------------------------------------------ function setup_as_single_rate(block,clkname,cename) inputRates = block.inputRates; uniqueInputRates = unique(inputRates); if (length(uniqueInputRates)==1 & uniqueInputRates(1)==Inf) block.addError('The inputs to this block cannot all be constant.'); return; end if (uniqueInputRates(end) == Inf) hasConstantInput = true; uniqueInputRates = uniqueInputRates(1:end-1); end if (length(uniqueInputRates) ~= 1) block.addError('The inputs to this block must run at a single rate.'); return; end theInputRate = uniqueInputRates(1); for i = 1:block.numSimulinkOutports block.outport(i).setRate(theInputRate); end block.addClkCEPair(clkname,cename,theInputRate); return; % ------------------------------------------------------------ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% I searched fairly extensively through the archive, and I saw no documentation of this. The Xilinx documentation helped a bit, but discrepancies between it and what Matlab would actually accept caused me many headaches. In the end I found the workaround above which seemed to work, but I'll admit I don't like it very much. Is anyone else working in this sort of an environment? Is there any reason that VHDL / Verilog seems to have been abandoned in favour of the Simulink-based block approach? Would anyone find it helpful if the tutorials were expanded a bit with this kind of information? Regards, James
