Hi Nishanth, Clearly your multiply and divide parameters are not what you expect them to be. The VCO frequency, needs to be between 600MHz and 1200MHz. VCO freq equals input freq * Multiply Parameter. Make sure that it falls within the correct range.
If you are changing the CASPER tools then you will need to have a look as the scripts that calculate and set the Multiply and Divide parameters on the VCO. Regards Wes Wesley New South African SKA Project +2721 506 7365 www.ska.ac.za On Thu, Feb 12, 2015 at 8:41 PM, Nishanth Shivashankaran <nshiv...@asu.edu> wrote: > Hi All, > > I am trying to create a yellow block for the roach2 with the MUSIC > adc/dac, I replaced the DCM with the MMCM. I compiled the DAC and ADC > portion separately. The DAC portion seems to work without any errors and I > was able to put out tones and i visually saw it on the spectrum analyzer > but the ADC portion is giving me some compilation error with the same clock > frequency. I am using the same set of multipliers and dividers as the DAC. > the error message says the ngdbuild is changing multipliers and dividers. I > am wondering if anyone can help me with this problem. > > ERROR:LIT:667 - Block 'MMCM_ADV symbol > > "physical_group_tut3_r2_adcdac_512_adc_mkid/tut3_r2_adcdac_512_adc_mkid/dcm_c > lk/tut3_r2_adcdac_512_adc_mkid/tut3_r2_adcdac_512_adc_mkid/MMCM_adc"' > has its > target frequency, FVCO, out of range. Valid FVCO range for speed grade > "-1" > is 600MHz - 1200MHz. The computed FCVO is a function of the input > frequency > CLKIN1_PERIOD, the division factor DIVCLK_DIVIDE, and the > CLKFBOUT_MULT_F > attribute (FVCO = 1000*CLKFBOUT_MULT_F/(CLKIN1_PERIOD*DIVCLK_DIVIDE)). > The > CLKIN_PERIOD attribute may have been set by ngdbuild based on the user > specified PERIOD constraint. The current calculated FVCO is 512.032770 > MHz. > Reference the V6 architecture Users Guide or search the Xilinx Answer > Records > database for the error code. > Errors found during logical drc. > > thanks > Nishanth Shivashankaran > >
