Anyone help? I'm working in academia and need to build a 300-receiver channel single-bit digitiser / cross-correlator with a single frequency channel having a bandwidth of 300 MHz, centre frequency ~3 GHz. The single bit digitisers sample I&Q giving a total data rate of 180 Gbps and using XOR gates to do the cross-correlations, the total computation rate is 54 T XOR operations per second. I need to accumulate cross-correlations typically for times ranging from 10 ms to a few seconds. The system would comprise an array of single bit digitisers linked via a high speed data bus to FPGA boards for the cross-correlation/accumulation. I've no skills in board design but could probably learn VHDL. I don't have funding to commission a design and build but wondered if anyone in this community could advise how I should go about building this system at our university.
Thank you for any help you can provide. Neil "Before acting on this email or opening any attachments you should read the Manchester Metropolitan University email disclaimer available on its website http://www.mmu.ac.uk/emaildisclaimer "
