Hi Michael, Which version (git commit and fork) of mlib_devel did you use to compile your bitcode?
Which version (git commit and fork) of the adc5g library are you using? What does the output of the following command show for the affected ADC after test mode has been unset? >>> adc5g.get_spi_control(roach2, zdok_n) Where roach2 is the FpgaClient instance and zdok_n is the ZDOK number of the affected ADC. Thanks, Rurik On Wed, Dec 7, 2016 at 11:28 AM, Michael D'Cruze < michael.dcr...@postgrad.manchester.ac.uk> wrote: > Dear all, > > > > I have a somewhat serious issue in that my adc5g seems to have become > stuck in test mode… > > I’ve messed around a bit with the very many functions within the > calibrate_all_delays top-level function, and can see that the spi_registers > are acknowledging set_test_mode and unset_test_mode, but in any case the > output time stream indicates unset_test_mode is ineffective beyond this. > > > > I’d be grateful for any suggestions to remedy this – I can’t see this > issue discussed on the mailing list. > > > > Cheers > > Michael >
