Hi Arjuna Thanks, that sounds very useful. I'll get in touch with Viduneth!
Regards Danny On Wed, Jan 11, 2017 at 2:44 PM, Madanayake,Habarakada Liyanachchi < arj...@uakron.edu> wrote: > Hi Danny, > > > We are working on FPGA implementations of tunable fractional delay blocks > based on Thiran IIR filters. They are very low complexity implementations. > If you are interested, we will be happy to share. I CC'd my PhD student > Viduneth who is working on Thiran based beamformers. > > > Thanks, > > Arjuna > > > > > Arjuna Madanayake > Associate Professor > ECE, University of Akron > Tel: 330-972-8461 <(330)%20972-8461> (W) 330-957-8704 <(330)%20957-8704> > (M) > http://blogs.uakron.edu/aspc-lab > http://blogs.uakron.edu/dharma > > "We wish to pursue the truth no matter where it leads; but to find the > truth we need imagination and skepticism both. We will not be afraid to > speculate, but we will be careful to distinguish speculation from fact. The > Cosmos is full beyond measure of elegant truths, of exquisite > interrelationships, of the awesome machinery of nature.” - Carl Sagan > > > > ------------------------------ > *From:* casper-boun...@lists.berkeley.edu <casper-bounces@lists. > berkeley.edu> on behalf of Daniel C Price <dan...@berkeley.edu> > *Sent:* Wednesday, January 11, 2017 5:22 PM > *To:* casper lists.berkeley.edu > *Subject:* [casper] Programmable fractional delay block > > Hi all > > Does anyone have an implementation of a runtime-programmable fractional > delay simulink block (e.g. 1/10th of a clock cycle) that they would be > willing to share? > > Regards > Danny > > -- > Danny Price | dan...@berkeley.edu | +1 617-386-3700 <(617)%20386-3700> > -- Danny Price | dan...@berkeley.edu | +1 617-386-3700
