Hi Jack, Thanks for the reply.
The design compiled for 260 MHz (adc0_clk) with yellow block set to 65 MHz. However, I am not yet clear about the external clock input requirements. Regards, Kaushal On 1/2/17, Jack Hickish <jackhick...@gmail.com> wrote: > Hi Kaushal, > > On Mon, 2 Jan 2017 10:16 am Kaushal Buch, <kaushal.b...@gmail.com> wrote: > >> Dear all, >> >> We have interfaced 64-channel ADC with ROACH-1 board and it is working >> as expected using on-board clock (50MHz). There is provision to >> provide an external clock to this board to operate ADC to get a >> maximum data rate of 65 MSPS. However, we have a few queries and need >> inputs on the following: >> >> 1. What should be the power level for the external clock ? >> > > If I remember correctly, I believe it takes an LVPECL input. > > > >> 2. On the ROACH-1 side, we have x64-adc yellow block interface where >> we can set the ADC clock rate. Should we enter 65MHz over there? Will >> the default yellow block support this ? >> > > Yes, set the yellow block to 65MHz. I doubt anyone has tried this, so while > it should work, maybe you'll encounter some timing problems. > > > >> 3. If x64_adc is operated at 65MHz clock, ROACH-1 has to be operated >> at 4 times the ADC clock i.e. 260MHz. Should XSG_core_config settings, >> 'arb_clk' be set to 260 MHz? As 'arb_clk' is derived from internal >> clock using DCM, how is the stability of 'arb_clk' at 260MHz? Has >> anyone used this ? >> > > You want adc0_clk, set to 260MHz. > > Cheers, > > Jack > > >> >> Thanks & Regards, >> >> Kaushal >> >> >
