Hi Wes and other SKARAB experts,
To my understanding our SKARAB is now "bricked" and no longer responds on
Ethernet at all. We now need a way to bring it back to life from a straight
off the factory floor state. We surmise this involves JTAG and while there
is a tantalizing mention of this protocol in the docs Adam supplied, there
are no details.
We may need Peralex expert support here. We are time constrained on this
project and need to get rolling.
Please advise, thanks!
Jonathan Weintroub
SAO
On Wed, Jun 14, 2017 at 5:11 PM Wesley New <wes...@ska.ac.za> wrote:
> Hi Mark,
>
> Firstly, welcome to the CASPER community.
>
> The SKARAB has multiple images stored in Flash. These are meant only used
> for the initial FPGA image at start up and a fall back image. This is a
> Xilinx standard method of configuration. You should be using the
> upload_to_ram_and_program function. This function uploads the your compiled
> fpg file to the SDRAM and then triggers the Virtex to program itself from
> the SDRAM. You will probably have overwritten the boot images. :(
>
> import casperfpga
>
> SKARAB_IP = '10.99.45.170'
> SKARAB_FPG = 'skarab.fpg'
>
> # skarab programming
> skarab = casperfpga.CasperFpga(SKARAB_IP)
> skarab.upload_to_ram_and_program(SKARAB_FPG)
>
> Does the board come back after waiting some time?
>
>
>
>
> Wesley New
> South African SKA Project
> +2721 506 7300
> www.ska.ac.za
>
>
>
> On Wed, Jun 14, 2017 at 7:16 PM, Peryer, Mark A. <
> mark.per...@cfa.harvard.edu> wrote:
>
>> Hello,
>>
>> After trying to reconfigure the flash memory on the Virtex7 FPGA with a
>> new image, I am no longer able to connect to the SKARAB through casperfpga
>> using the 1GigE port. When I enter the command fpga =
>> casperfpga.SkarabFpga('169.254.128.213'), the following is output.
>>
>> DEBUG:casperfpga.casperfpga:169.254.128.213: now a CasperFpga
>> DEBUG:casperfpga.skarab_fpga:Retransmit attempts: 0
>> DEBUG:casperfpga.skarab_fpga:Waiting for response.
>> DEBUG:casperfpga.skarab_fpga:No packet received: will retransmit
>> DEBUG:casperfpga.skarab_fpga:Retransmit attempts: 1
>> DEBUG:casperfpga.skarab_fpga:Waiting for response.
>> DEBUG:casperfpga.skarab_fpga:No packet received: will retransmit
>> DEBUG:casperfpga.skarab_fpga:Retransmit attempts: 2
>> DEBUG:casperfpga.skarab_fpga:Waiting for response.
>> DEBUG:casperfpga.skarab_fpga:No packet received: will retransmit
>> ERROR:casperfpga.skarab_fpga:Socket timeout. Response packet not received.
>>
>> My thinking is that the firmware image loaded into the flash is corrupt
>> and now the 1GigE port is disabled. Are these any other possible ways to
>> load a firmware image into flash without using the 1GigE port, such as the
>> USB port or JTAG header? If so, what would be the required procedure to do
>> so?
>>
>> Thanks,
>>
>> Mark Peryer
>>
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