Hello Andrew,
​
I also made a block similar to yours using two single port ram. Some small 
delay values need to be adjusted. I tried to open your .slx design file. It has 
some broken links and I tried to remove them and ran a simulation but I am not 
getting the output as expected. May be during Intialisation something going 
wrong and creating the broken link. Can you please check.

Hello Jack , David
Thanks for your inputs.
Indrajit Barve
indra...@iiap.res.in (mailto:indra...@iiap.res.in)
080-22541492 (tel:080-22541492)

On Apr 25 2019, at 6:12 pm, Andrew Martens <and...@ska.ac.za> wrote:
> Hi Indrajit
>
> This should do something like what you want to do I think.
> Cheers
> Andrew
>
>
> On Thu, Apr 25, 2019 at 6:53 AM Indrajit Barve <indra...@iiap.res.in 
> (mailto:indra...@iiap.res.in)> wrote:
> > Hello all,
> >
> > I would like to implement a FIFO with input port data type depth and width 
> > of 2048 X 32 and output port data type 1024 X 64. Basically looking a 
> > similar module like this 
> > https://www.xilinx.com/support/documentation/application_notes/xapp261.pdf 
> > . or how to implement / configure Data-Width Conversion for a FIFO on 
> > ROACH1 .
> > Thanks
> > Indrajit
> >
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