Hi Heystek,

Somewhere in your design -- presumably outside the screenshot you just sent
or inside one of your blocks -- you have a "Gateway In" block. This isn't
allowed (when you compile the design, the toolflow doesn't know what to
drive it with). If you find and delete this block, I think you'll be good
to go.

Cheers
Jack

On Tue, 11 Aug 2020 at 14:39, Heystek Grobler <heystekgrob...@gmail.com>
wrote:

> Hey James
>
> Below is a snipped:
>
>
>
> On 11 Aug 2020, at 15:24, James Smith <jsm...@ska.ac.za> wrote:
>
> Send a screen snip of what you've got, Heystek?
>
> On Tue, Aug 11, 2020 at 1:22 PM Heystek Grobler <heystekgrob...@gmail.com>
> wrote:
>
>> Hey James and Mugundhan
>>
>> Thank you for your emails.
>>
>> Yes, I have a Shared BRAM block in my design. The BRAM block is from the
>> casper blockset. So I should rather use something else for the design?
>>
>> On 11 Aug 2020, at 15:03, James Smith <jsm...@ska.ac.za> wrote:
>>
>> Hello Heystek,
>>
>> Somewhere in your design, you are trying to use a Xilinx block as an
>> input. Replace it with one of the yellow blocks from the Casper tools, and
>> you should be okay. (Usually this will be a software register or a BRAM
>> block.)
>>
>> Regards,
>> James
>>
>>
>> On Tue, Aug 11, 2020 at 12:54 PM Heystek Grobler <
>> heystekgrob...@gmail.com> wrote:
>>
>>> Good day everyone
>>>
>>> I am compiling a design for Roach2. I can into this error when running
>>> casper_xps:
>>>
>>> "xilinx input gateways cannot be used in a design. Only gpio blocks”
>>>
>>> How can I solve this or am I doing something stupid?
>>>
>>> Thanks for the help
>>>
>>> Heystek
>>>
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