Hi Neil,

For your 1-bit correlation, are you going to implement a lag correlator?

If so, then your logic could be:

  *   ISERDES operating at 1Gbps sampling the complex-valued baseband
  *   4-bits at 250MHz or 8-bits at 125MHz inside the FPGA
  *   Logic to perform 4-bits or 8-bits digital delay line
  *   Logic for 4 or 8 times 1-bit complex-valued correlation and averaging of 
those 4 or 8-bit samples
  *   If you offset your product table so the answers in the table are all 
positive, then you just need an accumulator for your correlation lags
  *   At this point you have correlation products that will generate a 
carry-out at a slow-rate, so you can count those using a carry in on a counter.
  *   You can further decimate the carries, eg., divide-by-2 or 4 to bring the 
clock rate of the counter down to say 125MHz/4  ~ 30MHz

A 4-bit x 4-bit correlator will have 16 inputs (4-bits I + Q for two inputs), 
but FPGA LUTs have 6-inputs, so you will use 3 LUTs for the inputs plus another 
LUT to combine the results of that, so call it 4 LUTs to get each bit of your 
4-bit correlation. If you do some form of deleted-inner-product (like used on 
2-bit correlators) you can probably get away with a 3-bit or 4-bit product, 
which you would register and average … so 16 LUTs and 4 registers for each 
correlation cell.

If your dump rate is say 1s, then at 1GHz sample rate, your number of samples 
is 1G. The number of bits you need in your correlation and accumulation logic 
is log2(1G) = 30-bits, but since the SNR improvement is sqrt(N), so the minimum 
number of bits you want to keep in the accumulation is about 15-bits, i.e., the 
15 MSBs of that accumulator. That means you don’t have to read the LSBs that 
are implemented in the correlation logic, and is the reason why counting the 
carry-out from that logic works fine.

So ….

  *   16 LUTs + 4-registers in each correlation cell
  *   26 more bits in the accumulation logic
Scaled by the number of lags in your correlation result.

Another option to consider, is to use a high-speed transceiver, sample at say 
16Gbps, digitally downconvert and filter the 8GHz of real-valued sampled 
bandwidth down to 2GHz, and that oversampling-by-4 will give you 6dB 
improvement in SNR, so you can implement a 2-bit correlator on the result.

The tradeoff will be a whole lot of LVDS inputs at 1Gbps vs a whole lot of 
transceiver inputs at 16Gbps.

1-bit correlation using high-speed transceivers has been demonstrated by a 
number of people on this list. You just need to force the transceiver into 
lock-to-reference mode to ensure it operates like a synchronous sampler (rather 
than letting the clock-and-data recovery unit track the phase of an incoming 
data stream).

Regards,
Dave

From: salmon.na via casper@lists.berkeley.edu <casper@lists.berkeley.edu>
Sent: Saturday, November 11, 2023 11:48 AM
To: casper@lists.berkeley.edu
Subject: [EXTERNAL] [casper] state of the art single bit correlators

For a paper on non-radioastronomy aperture synthesis technology I need to know 
how many receiver channels can run into an almost top of the range FPGA 
optimally designed single-bit cross-correlator running a 2 Gbps. So each 
receiver is digitised (sine and cosine) in single bits 1 Gbps. I’m wondering if 
there are scaling laws for this and I only need to have a ball park figure, ie 
a precision of say a factor of three or thereabouts. Any associate papers 
related to that which might have clues to the capabilities would be helpful.

Many thanks,
Neil Salmon
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