Author: Craig Topper Date: 2024-01-22T20:17:36-08:00 New Revision: 904b0901ef2d33e6232b7a51fa2525c30fd117e8
URL: https://github.com/llvm/llvm-project/commit/904b0901ef2d33e6232b7a51fa2525c30fd117e8 DIFF: https://github.com/llvm/llvm-project/commit/904b0901ef2d33e6232b7a51fa2525c30fd117e8.diff LOG: [RISCV] Add FeatureFastUnalignedAccess to sifive-p450. (#79075) Added: Modified: clang/test/Preprocessor/riscv-target-features.c llvm/lib/Target/RISCV/RISCVProcessors.td Removed: ################################################################################ diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 5fde5ccdbeacfb..39d2c66f14b23f 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -1400,4 +1400,6 @@ // RUN: -munaligned-access -o - | FileCheck %s --check-prefix=CHECK-MISALIGNED-FAST // RUN: %clang --target=riscv64-unknown-linux-gnu -march=rv64i -E -dM %s \ // RUN: -munaligned-access -o - | FileCheck %s --check-prefix=CHECK-MISALIGNED-FAST +// RUN: %clang --target=riscv64-unknown-linux-gnu -mcpu=sifive-p450 -E -dM %s \ +// RUN: -o - | FileCheck %s --check-prefix=CHECK-MISALIGNED-FAST // CHECK-MISALIGNED-FAST: __riscv_misaligned_fast 1 diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index db60a5a1dab002..af621de9f802aa 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -238,7 +238,8 @@ def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model, FeatureStdExtZba, FeatureStdExtZbb, FeatureStdExtZbs, - FeatureStdExtZfhmin], + FeatureStdExtZfhmin, + FeatureFastUnalignedAccess], [TuneNoDefaultUnroll, TuneConditionalCompressedMoveFusion, TuneLUIADDIFusion, _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits