I think this patch is the same as yours, but with some commented out
code removed.
I made some white space changes to the s2881 so that it would be
easier to see your changes to devicetree.cb.
When you send patches to the list, you should add a Signed-off-by:
line, even if it isn't ready to be committed. I'm not adding one
because it's your patch :)
Thanks,
Myles
Index: svn/src/mainboard/hp/Kconfig
===================================================================
--- svn.orig/src/mainboard/hp/Kconfig
+++ svn/src/mainboard/hp/Kconfig
@@ -2,6 +2,7 @@ choice
prompt "Mainboard model"
depends on VENDOR_HP
+source "src/mainboard/hp/dl145_g1/Kconfig"
source "src/mainboard/hp/dl145_g3/Kconfig"
source "src/mainboard/hp/e_vectra_p2706t/Kconfig"
Index: svn/src/mainboard/hp/dl145_g1/Kconfig
===================================================================
--- svn.orig/src/mainboard/hp/dl145_g1/Kconfig
+++ svn/src/mainboard/hp/dl145_g1/Kconfig
@@ -1,5 +1,5 @@
-config BOARD_TYAN_S2881
- bool "S2881 (Thunder K8SR)"
+config BOARD_HP_DL145_G1
+ bool "ProLiant DL145 G1"
select ARCH_X86
select CPU_AMD_SOCKET_940
select NORTHBRIDGE_AMD_AMDK8
@@ -13,65 +13,68 @@ config BOARD_TYAN_S2881
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select BOARD_ROMSIZE_KB_512
- select SB_HT_CHAIN_UNITID_OFFSET_ONLY
- select DRIVERS_SIL
config MAINBOARD_DIR
string
- default tyan/s2881
- depends on BOARD_TYAN_S2881
+ default hp/dl145_g1
+ depends on BOARD_HP_DL145_G1
config APIC_ID_OFFSET
hex
default 0x0
- depends on BOARD_TYAN_S2881
+ depends on BOARD_HP_DL145_G1
config SB_HT_CHAIN_ON_BUS0
int
default 2
- depends on BOARD_TYAN_S2881
+ depends on BOARD_HP_DL145_G1
config MAINBOARD_PART_NUMBER
string
- default "S2881"
- depends on BOARD_TYAN_S2881
+ default "ProLiant DL145 G1"
+ depends on BOARD_HP_DL145_G1
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x1022
+ depends on BOARD_HP_DL145_G1
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex
- default 0x2881
- depends on BOARD_TYAN_S2881
+ default 0x1451
+ depends on BOARD_HP_DL145_G1
config HW_MEM_HOLE_SIZEK
hex
default 0x100000
- depends on BOARD_TYAN_S2881
+ depends on BOARD_HP_DL145_G1
config MAX_CPUS
int
default 4
- depends on BOARD_TYAN_S2881
+ depends on BOARD_HP_DL145_G1
config MAX_PHYSICAL_CPUS
int
default 2
- depends on BOARD_TYAN_S2881
+ depends on BOARD_HP_DL145_G1
config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n
- depends on BOARD_TYAN_S2881
+ depends on BOARD_HP_DL145_G1
config HT_CHAIN_UNITID_BASE
hex
- default 0xa
- depends on BOARD_TYAN_S2881
+ default 0x1
+ depends on BOARD_HP_DL145_G1
config HT_CHAIN_END_UNITID_BASE
hex
default 0x6
- depends on BOARD_TYAN_S2881
+ depends on BOARD_HP_DL145_G1
config IRQ_SLOT_COUNT
int
- default 9
- depends on BOARD_TYAN_S2881
+ default 12
+ depends on BOARD_HP_DL145_G1
Index: svn/src/mainboard/hp/dl145_g1/devicetree.cb
===================================================================
--- svn.orig/src/mainboard/hp/dl145_g1/devicetree.cb
+++ svn/src/mainboard/hp/dl145_g1/devicetree.cb
@@ -11,26 +11,23 @@ chip northbridge/amd/amdk8/root_complex
device pci 18.0 on # link 2
chip southbridge/amd/amd8131
# the on/off keyword is mandatory
- device pci 0.0 on
- device pci 9.0 on end # Broadcom 5704
- device pci 9.1 on end
- device pci a.0 on end # Adaptic
- device pci a.1 on end
- end
+ device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
+ device pci 2.0 on end
+ device pci 2.1 on end
+ device pci 3.0 off end
end
chip southbridge/amd/amd8111
# this "device pci 0.0" is the parent the next one
# PCI bridge
device pci 0.0 on
- device pci 0.0 on end
- device pci 0.1 on end
- device pci 0.2 off end
+ device pci 0.0 on end # LPC
+ device pci 0.1 on end # IDE
+ device pci 0.2 on end # SMbus
+ device pci 0.3 on end # ACPI
device pci 1.0 off end
- device pci 5.0 on end # SiI
- device pci 6.0 on end
end
device pci 1.0 on
chip superio/winbond/w83627hf
@@ -57,17 +54,11 @@ chip northbridge/amd/amdk8/root_complex
irq 0x70 = 1
irq 0x72 = 12
end
- device pnp 2e.6 off # CIR
- io 0x60 = 0x100
- end
- device pnp 2e.7 off # GAME_MIDI_GIPO1
- io 0x60 = 0x220
- io 0x62 = 0x300
- irq 0x70 = 9
- end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GAM_MIDI_GIPO1
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
- device pnp 2e.a off end # ACPI
+ device pnp 2e.a on end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
irq 0x70 = 5
Index: svn/src/mainboard/hp/dl145_g1/romstage.c
===================================================================
--- svn.orig/src/mainboard/hp/dl145_g1/romstage.c
+++ svn/src/mainboard/hp/dl145_g1/romstage.c
@@ -123,7 +123,7 @@ void cache_as_ram_main(unsigned long bis
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- setup_s2881_resource_map();
+ setup_dl145g1_resource_map();
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
Index: svn/src/mainboard/hp/dl145_g1/mptable.c
===================================================================
--- svn.orig/src/mainboard/hp/dl145_g1/mptable.c
+++ svn/src/mainboard/hp/dl145_g1/mptable.c
@@ -23,8 +23,8 @@ extern unsigned sbdn3;
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
- static const char oem[8] = "COREBOOT";
- static const char productid[12] = "S2881 ";
+ static const char oem[8] = "FOI ";
+ static const char productid[12] = "DL145G1 ";
struct mp_config_table *mc;
unsigned char bus_num;
@@ -62,7 +62,7 @@ static void *smp_write_config_table(void
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000);
+ smp_write_ioapic(mc, apicid_8111, 0x20, 0xfec00000);
{
device_t dev;
struct resource *res;
@@ -70,14 +70,14 @@ static void *smp_write_config_table(void
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_1, 0x20, res->base);
}
}
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_2, 0x20, res->base);
}
}
@@ -86,41 +86,25 @@ static void *smp_write_config_table(void
mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-//8111 LPC ????
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|0, apicid_8111, 0x13);
-
-//On Board AMD USB ???
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
-
-//On Board ATI Display Adapter
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12);
-
-//On Board SI Serial ATA
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x11);
-
-//Slot 3 PCIX 100/66
- for(i=0;i<4;i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (3+i)%4); //27
- }
-
-//On Board NIC and adaptec scsi
- for(i=0;i<2;i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|i, apicid_8131_1, (0+i)%4); //24
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|i, apicid_8131_1, (0+i)%4); //24
- }
-
-//Slot 1 PCI-X 133/100/66 or Side 1 on raiser card
- for(i=0;i<4;i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|i, apicid_8131_2, (0+i)%4); //28
- }
-
- //Slot 1 PCI-X 133/100/66, Side 2 on raiser card
- //Fix ME, IRQ Pins?
- for(i=0;i<4;i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (1+i)%4); //28
- }
-
-
+ // Integrated SMBus 2.0
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|3, apicid_8111 , 0x13);
+ // Integrated AMD AC97 Audio
+ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11);
+ // Integrated AMD USB
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x0 <<2)|3, apicid_8111 , 0x12);
+ // On board ATI Rage XL
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x10);
+ // On board Broadcom nics
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|0, apicid_8131_2, 0x03);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|1, apicid_8131_2, 0x00);
+ // On board LSI SCSI
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02);
+
+ // PCIX Slot
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|0, apicid_8131_1, 0x1);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x2);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x3);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x4);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
Index: svn/src/mainboard/hp/dl145_g1/irq_tables.c
===================================================================
--- svn.orig/src/mainboard/hp/dl145_g1/irq_tables.c
+++ svn/src/mainboard/hp/dl145_g1/irq_tables.c
@@ -51,7 +51,7 @@ unsigned long write_pirq_routing_table(u
uint8_t sum=0;
int i;
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
+ get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and acpi_tables.c
/* Align the table to be 16 byte aligned. */
addr += 15;
Index: svn/src/mainboard/hp/dl145_g1/resourcemap.c
===================================================================
--- svn.orig/src/mainboard/hp/dl145_g1/resourcemap.c
+++ svn/src/mainboard/hp/dl145_g1/resourcemap.c
@@ -1,9 +1,9 @@
/*
- * Tyan S2881 needs a different resource map
+ * DL145G1 needs a different resource map
*
*/
-static void setup_s2881_resource_map(void)
+static void setup_dl145g1_resource_map(void)
{
static const unsigned int register_values[] = {
/* Careful set limit registers before base registers which contain the enables */
Index: svn/src/mainboard/hp/dl145_g1/mainboard.c
===================================================================
--- svn.orig/src/mainboard/hp/dl145_g1/mainboard.c
+++ svn/src/mainboard/hp/dl145_g1/mainboard.c
@@ -24,5 +24,5 @@
#include "chip.h"
struct chip_operations mainboard_ops = {
- CHIP_NAME("Tyan S2881 Mainboard")
+ CHIP_NAME("HP DL145G1 Mainboard")
};
--
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