Faulty CPUs are truly rare... But recently while building the A88XM-E
coreboot test stand (more info at [1] "ProTip: buy a 5.25" fan
controller while you still can" link below) ---> I got a used A10-6700
online for a dirt cheap price: the listing looked nice - a clear photo
without any bent pins - but there was an intriguing note "one RAM slot
doesn't work". So I thought:
> That looks like a motherboard problem! Or something related to the seller's
> RAM sticks: either a faulty stick or a badly mismatching pair. Shouldn't
> happen on my spare well-tested A88XM-E with a known good RAM, especially with
> a beautiful coreboot replacing the crappy proprietary UEFI, so lets save a
> few bucks "
However, I ran into the same problem: the board boots fine to OS but
sees just one of two BLT8G3D1869DT1TX0 8GB RAM sticks, regardless if I
use the XMP profile to run them at 1866MHz CL9 (
CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1 stuff which I created two years ago
- [2] ) or keep them at turtle 1333Mhz CL9. Here are the most
interesting AGESA events which happen while trying to initialize the
RAM:
*) WARNING Event: 04012100 Data: 0, 0, 0, 0 [0m ; AGESA.h tells:
#define MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED 0x04012100ul ///<
Channel Interleaveing Requested, but could not be enabled
*) WARNING Event: 04012200 Data: 0, 0, 0, 0 [0m ; AGESA.h tells:
#define MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED 0x04012200ul ///<
Bank Interleaveing Requested, but could not be enabled
*) ERROR Event: 04010300 Data: 0, 0, 0, 0 [0m ; AGESA.h tells:
#define MEM_ERROR_NO_DQS_POS_RD_WINDOW 0x04010300ul ///< No DQS
Position window for RD DQS
See the full AGESA log here - https://pastebin.com/FLWFk9SF . Please
keep in mind that, if I replace this with another (bought later)
A10-6700 - using the same A88XM-E / RAM / coreboot / OS - then
everything works fine. So it's clearly a CPU problem, but may be
possible to avoid from the firmware side...
Do you think it's possible to workaround this problem (no matter how
dirty the hack) from AGESA side and get this CPU working with both
sticks? Is there anything I could try before giving up and making a
DIY keychain or whatever? Any ideas?
[1]
https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/message/RDMSYKLAYZOSUXOMCZSXVGGQAOYQEV5A/
- " ProTip: buy a 5.25" fan controller while you still can "
[2] https://review.coreboot.org/c/coreboot/+/40488 -
vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
--
Best regards, Mike Banon
Open Source Community Manager of 3mdeb - https://3mdeb.com/
[0m[SPEW ] AmdInitEarly: End[0m
[0m
[0m[INFO ] Timestamp - back from AmdInitEarly: 7808722251[0m
[0m[DEBUG] AmdInitEarly() returned AGESA_SUCCESS[0m
[0m[DEBUG] APIC 00: Heap in LocalCache (2) at 0x00400000[0m
[0m[DEBUG] APIC 00: ** Exit AmdInitEarly [00020002][0m
[0m[INFO ] Timestamp - before RAM initialization: 7892186693[0m
[0m
[0m[DEBUG] APIC 00: ** Enter AmdInitPost [00020006][0m
[0m[INFO ] Timestamp - calling AmdInitPost: 7939035677[0m
[0m[SPEW ] AmdInitPost: Start[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0[0m
[0m
[0m[SPEW ] AmdMemAuto: Start[0m
[0m[SPEW ] F15TnGetPstateFrequency - P3[0m
[0m[SPEW ] FrequencyInMHz=3700, CpuFid=21, CpuDid=0[0m
[0m[SPEW ] -------------READING SPD-----------[0m
[0m[SPEW ] iobase: 0x00000B00, SmbusSlave: 0x000000A0, count: 256[0m
[0m
[0m[SPEW ] -------------FINISHED READING SPD-----------[0m
[0m[SPEW ] -------------READING SPD-----------[0m
[0m[SPEW ] iobase: 0x00000B00, SmbusSlave: 0x000000A2, count: 256[0m
[0m
[0m[SPEW ] -------------FINISHED READING SPD-----------[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: 1247000, 0, 0, 0[0m
[0m
[0m[SPEW ] F15TnGetNbPstateInfo - NB P3[0m
[0m[SPEW ] F15TnGetNbPstateInfo - NB P2[0m
[0m[SPEW ] F15TnGetNbPstateInfo - NB P1[0m
[0m[SPEW ] F15TnGetNbPstateInfo - NB P0[0m
[0m[SPEW ] En:1 Fid:c Did:0 Vid:3e[0m
[0m[SPEW ] F15TnGetNbFreqNumeratorInMHz - NbFid=12[0m
[0m[SPEW ] FreqNumeratorInMHz=1600[0m
[0m[SPEW ] F15TnGetNbFreqDivisor - NbDid=0[0m
[0m[SPEW ] FreqDivisor=1[0m
[0m[SPEW ] F15TnCovertVidInuV[0m
[0m[SPEW ] Vid=3e, VoltageInuV=1162500[0m
[0m[SPEW ] NB Pstate 0 is Valid. NbVid=62 VoltageInuV=1162500[0m
[0m[SPEW ] F15TnGetNbPstateInfo - NB P3[0m
[0m[SPEW ] F15TnGetNbPstateInfo - NB P2[0m
[0m[SPEW ] F15TnGetNbPstateInfo - NB P1[0m
[0m[SPEW ] F15TnGetNbPstateInfo - NB P0[0m
[0m[SPEW ] En:1 Fid:c Did:0 Vid:3e[0m
[0m[SPEW ] F15TnGetNbFreqNumeratorInMHz - NbFid=12[0m
[0m[SPEW ] FreqNumeratorInMHz=1600[0m
[0m[SPEW ] F15TnGetNbFreqDivisor - NbDid=0[0m
[0m[SPEW ] FreqDivisor=1[0m
[0m[SPEW ] F15TnCovertVidInuV[0m
[0m[SPEW ] Vid=3e, VoltageInuV=1162500[0m
[0m[SPEW ] NB Pstate 0 is Valid. NbVid=62 VoltageInuV=1162500[0m
[0m[SPEW ] F15TnGetNbPstateInfo - NB P0[0m
[0m[SPEW ] En:1 Fid:c Did:0 Vid:3e[0m
[0m[SPEW ] F15TnGetNbFreqNumeratorInMHz - NbFid=12[0m
[0m[SPEW ] FreqNumeratorInMHz=1600[0m
[0m[SPEW ] F15TnGetNbFreqDivisor - NbDid=0[0m
[0m[SPEW ] FreqDivisor=1[0m
[0m[SPEW ] F15TnCovertVidInuV[0m
[0m[SPEW ] Vid=3e, VoltageInuV=1162500[0m
[0m[SPEW ] NB Pstate 0 is Valid. NbVid=62 VoltageInuV=1162500[0m
[0m[SPEW ] F15TnGetPstateFrequency - P3[0m
[0m[SPEW ] FrequencyInMHz=3700, CpuFid=21, CpuDid=0[0m
[0m
[0m[SPEW ] * ERROR Event: 04010300 Data: 0, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * ERROR Event: 04010300 Data: 0, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * ERROR Event: 04010300 Data: 0, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * ERROR Event: 04010300 Data: 0, 0, 0, 0[0m
[0m
[0m[SPEW ] F15TnGetNbPstateInfo - NB P0[0m
[0m[SPEW ] En:1 Fid:c Did:0 Vid:3e[0m
[0m[SPEW ] F15TnGetNbFreqNumeratorInMHz - NbFid=12[0m
[0m[SPEW ] FreqNumeratorInMHz=1600[0m
[0m[SPEW ] F15TnGetNbFreqDivisor - NbDid=0[0m
[0m[SPEW ] FreqDivisor=1[0m
[0m[SPEW ] F15TnCovertVidInuV[0m
[0m[SPEW ] Vid=3e, VoltageInuV=1162500[0m
[0m[SPEW ] NB Pstate 0 is Valid. NbVid=62 VoltageInuV=1162500[0m
[0m[SPEW ] F15TnGetNbPstateInfo - NB P1[0m
[0m[SPEW ] F15TnGetNbPstateInfo - NB P2[0m
[0m[SPEW ] F15TnGetNbPstateInfo - NB P3[0m
[0m[SPEW ] F15TnGetPstateFrequency - P3[0m
[0m[SPEW ] FrequencyInMHz=3700, CpuFid=21, CpuDid=0[0m
[0m
[0m[SPEW ] * WARNING Event: 04012100 Data: 0, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * WARNING Event: 04012200 Data: 0, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: 1240000, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: 1241000, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: 1242000, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: 1243000, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: 1244000, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: 1245000, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: 1246000, 0, 0, 0[0m
[0m
[0m[SPEW ] AmdMemAuto: End[0m
[0m[SPEW ] AmdCpuPost: Start[0m
[0m[SPEW ] Dispatch CPU features after AP MTRR sync[0m
[0m[SPEW ] C6 is enabled[0m
[0m[SPEW ] Boost is enabled[0m
[0m[SPEW ] Cache flush on hlt feature is enabled[0m
[0m[SPEW ] HTC is being initialized[0m
[0m[SPEW ] HTC is enabled[0m
[0m[SPEW ] Perform feature leveling[0m
[0m[SPEW ] Create P-state info in the heap[0m
[0m[SPEW ] F15TnGetPstateMaxState[0m
[0m[SPEW ] MaxPStateNumber=7, NumBoostStates=3[0m
[0m[SPEW ] F15TnGetPstateMaxState[0m
[0m[SPEW ] MaxPStateNumber=7, NumBoostStates=3[0m
[0m[SPEW ] F15TnGetPstateRegisterInfo - P0[0m
[0m[SPEW ] Pstate 0 is enabled. SwPstateNumber=0[0m
[0m[SPEW ] IddVal=167, IddDiv=1[0m
[0m[SPEW ] F15TnGetPstateRegisterInfo - P1[0m
[0m[SPEW ] Pstate 1 is enabled. SwPstateNumber=1[0m
[0m[SPEW ] IddVal=197, IddDiv=1[0m
[0m[SPEW ] F15TnGetPstateRegisterInfo - P2[0m
[0m[SPEW ] Pstate 2 is enabled. SwPstateNumber=2[0m
[0m[SPEW ] IddVal=159, IddDiv=1[0m
[0m[SPEW ] F15TnGetPstateRegisterInfo - P3[0m
[0m[SPEW ] Pstate 3 is enabled. SwPstateNumber=0[0m
[0m[SPEW ] IddVal=121, IddDiv=1[0m
[0m[SPEW ] F15TnGetPstateFrequency - P3[0m
[0m[SPEW ] FrequencyInMHz=3700, CpuFid=21, CpuDid=0[0m
[0m[SPEW ] F15TnGetPstatePower - P3[0m
[0m[SPEW ] PowerInMw=14671, CpuVid=54, IddValue=121, IddDiv=1[0m
[0m[SPEW ] F15TnGetPstateRegisterInfo - P4[0m
[0m[SPEW ] Pstate 4 is enabled. SwPstateNumber=1[0m
[0m[SPEW ] IddVal=101, IddDiv=1[0m
[0m[SPEW ] F15TnGetPstateFrequency - P4[0m
[0m[SPEW ] FrequencyInMHz=3400, CpuFid=18, CpuDid=0[0m
[0m[SPEW ] F15TnGetPstatePower - P4[0m
[0m[SPEW ] PowerInMw=11615, CpuVid=64, IddValue=101, IddDiv=1[0m
[0m[SPEW ] F15TnGetPstateRegisterInfo - P5[0m
[0m[SPEW ] Pstate 5 is enabled. SwPstateNumber=2[0m
[0m[SPEW ] IddVal=77, IddDiv=1[0m
[0m[SPEW ] F15TnGetPstateFrequency - P5[0m
[0m[SPEW ] FrequencyInMHz=2700, CpuFid=11, CpuDid=0[0m
[0m[SPEW ] F15TnGetPstatePower - P5[0m
[0m[SPEW ] PowerInMw=8373, CpuVid=74, IddValue=77, IddDiv=1[0m
[0m[SPEW ] F15TnGetPstateRegisterInfo - P6[0m
[0m[SPEW ] Pstate 6 is enabled. SwPstateNumber=3[0m
[0m[SPEW ] IddVal=55, IddDiv=1[0m
[0m[SPEW ] F15TnGetPstateFrequency - P6[0m
[0m[SPEW ] FrequencyInMHz=2300, CpuFid=7, CpuDid=0[0m
[0m[SPEW ] F15TnGetPstatePower - P6[0m
[0m[SPEW ] PowerInMw=5362, CpuVid=92, IddValue=55, IddDiv=1[0m
[0m[SPEW ] F15TnGetPstateRegisterInfo - P7[0m
[0m[SPEW ] Pstate 7 is enabled. SwPstateNumber=4[0m
[0m[SPEW ] IddVal=36, IddDiv=1[0m
[0m[SPEW ] F15TnGetPstateFrequency - P7[0m
[0m[SPEW ] FrequencyInMHz=1800, CpuFid=2, CpuDid=0[0m
[0m[SPEW ] F15TnGetPstatePower - P7[0m
[0m[SPEW ] PowerInMw=3105, CpuVid=110, IddValue=36, IddDiv=1[0m
[0m[SPEW ] F15TnSetTscFreqSel[0m
[0m[SPEW ] Dispatch CPU features before Relinquishing control of APs[0m
[0m[SPEW ] Relinquish control of APs[0m
[0m[SPEW ] AmdCpuPost: End[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a021, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] AmdInitPost: End[0m
[0m
[0m[SPEW ] Heap transfer Start ...[0m
[0m
[0m[INFO ] Timestamp - back from AmdInitPost: 16828942462[0m
[0m[DEBUG] AmdInitPost() returned AGESA_ERROR[0m
[0m
[0m[DEBUG] EventLog: EventClass = 5, EventInfo = 4010300.[0m
[0m[DEBUG] Param1 = 0, Param2 = 0.[0m
[0m[DEBUG] Param3 = 0, Param4 = 0.[0m
[0m
[0m[DEBUG] EventLog: EventClass = 5, EventInfo = 4010300.[0m
[0m[DEBUG] Param1 = 0, Param2 = 0.[0m
[0m[DEBUG] Param3 = 0, Param4 = 0.[0m
[0m
[0m[DEBUG] EventLog: EventClass = 5, EventInfo = 4010300.[0m
[0m[DEBUG] Param1 = 0, Param2 = 0.[0m
[0m[DEBUG] Param3 = 0, Param4 = 0.[0m
[0m
[0m[DEBUG] EventLog: EventClass = 5, EventInfo = 4010300.[0m
[0m[DEBUG] Param1 = 0, Param2 = 0.[0m
[0m[DEBUG] Param3 = 0, Param4 = 0.[0m
[0m
[0m[DEBUG] EventLog: EventClass = 4, EventInfo = 4012100.[0m
[0m[DEBUG] Param1 = 0, Param2 = 0.[0m
[0m[DEBUG] Param3 = 0, Param4 = 0.[0m
[0m
[0m[DEBUG] EventLog: EventClass = 4, EventInfo = 4012200.[0m
[0m[DEBUG] Param1 = 0, Param2 = 0.[0m
[0m[DEBUG] Param3 = 0, Param4 = 0.[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: 1180000, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: 1080000, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: 1040000, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a008, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00f, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a00e, 0, 0, 0[0m
[0m
[0m
[0m[SPEW ] * BOUNDS_CHK Event: 08040100 Data: a010, 0, 0, 0[0m
[0m
[0m[DEBUG] APIC 00: Heap in TempMem (3) at 0x000b0000[0m
[0m[DEBUG] APIC 00: ** Exit AmdInitPost [00020006][0m
[0m[INFO ] Timestamp - after RAM initialization: 17423588451[0m
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