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Today's Topics:
1. DMA transfer from ARM RAM (Alexander Vasiliev)
2. Re: Capturing NTSC video (DVEM) (David A Kondrad)
3. RE: DMA transfer from ARM RAM (Monk, Roger)
4. RE: How to make CMEM cacheable on ARM side on DM6446?
(Ring, Chris)
----------------------------------------------------------------------
Message: 1
Date: Thu, 24 Jan 2008 16:54:20 +0300
From: "Alexander Vasiliev" <[EMAIL PROTECTED]>
Subject: DMA transfer from ARM RAM
To: davinci-linux-open-source@linux.davincidsp.com
Message-ID:
<[EMAIL PROTECTED]>
Content-Type: text/plain; charset=ISO-8859-1
Hello,
I want to use EDMA during booting. So i am testing data transfer from
ARM RAM to DRR2. Copying from DRR to arm goes fine. But during copying
from arm to ddr2, every (29-31)th bytes are broken. Any ideas?
As the base application i use spraai0-application. Here is the patch for it:
diff -uNr uartapp/dm644x.h Quartapp/dm644x.h
--- uartapp/dm644x.h 2006-11-15 13:39:28.000000000 +0300
+++ Quartapp/dm644x.h 2008-01-24 15:33:09.000000000 +0300
@@ -180,6 +180,72 @@
#define DDR_TEST_PATTERN 0xA55AA55Au
#define DDR_RAM_SIZE 0x10000000u
+/*----------------------------------------------------------------------------
+DMA register structure
+------------------------------------------------------------------------------*/
+
+#define DMA_REG_BASE 0x01C00000
/*base for dma registers*/
+
+#define PARAM_SET_BASE (DMA_REG_BASE + 0x4000)
/*base for PaRAM sets*/
+#define PARAM_SET_OFFSET 0x20
/*offset between PaRAM stes*/
+#define PARAM_SET(n) (PARAM_SET_BASE + n * PARAM_SET_OFFSET) /*PaRAM
set n*/
+
+#define DMA_DRAE (0x0340 + DMA_REG_BASE)
/*Region access
enable. low part*/
+#define DMA_DRAE_H (0x0344 + DMA_REG_BASE)
/*Region access
enable*. high part*/
+
+#define DMA_IPR (0x1068 + DMA_REG_BASE)
/*Interrupt pending
register. low part*/
+#define DMA_IPR_H (0x106C + DMA_REG_BASE)
/*Interrupt pending
register. high part*/
+
+#define DMA_EMR (0x0300 + DMA_REG_BASE)
/*Event missed. low part*/
+#define DMA_EMR_H (0x0304 + DMA_REG_BASE)
/*Event missed. high part*/
+
+#define DMA_CCERR (0x0318 + DMA_REG_BASE)
/*Error*/
+
+#define DMA_SER (0x1038 + DMA_REG_BASE)
/*Secondary event. low part*/
+#define DMA_SER_H (0x103C + DMA_REG_BASE)
/*Secondary event. high part*/
+
+#define DMA_SECR (0x1040 + DMA_REG_BASE)
/*Secondary event
clear. low part*/
+#define DMA_SECR_H (0x1044 + DMA_REG_BASE)
/*Secondary event
clear. high part*/
+
+#define DMA_ICR (0x1070 + DMA_REG_BASE)
/*Interrupt clear
register. low pert*/
+#define DMA_ICR_H (0x1074 + DMA_REG_BASE)
/*Interrupt clear
register. high part*/
+
+#define DMA_IESR (0x1060 + DMA_REG_BASE)
/*Interrupt set
enable. low part*/
+#define DMA_IESR_H (0x1064 + DMA_REG_BASE)
/*Interrupt set
enable. high part*/
+
+#define DMA_ESR (0x1010 + DMA_REG_BASE)
/*Event set. low part*/
+#define DMA_ESR_H (0x1014 + DMA_REG_BASE)
/*Event set. high part*/
+
+#define DMA_IPR_0 (0x2068 + DMA_REG_BASE)
/*Interrupt pending
register. low part. region 0*/
+#define DMA_IPR_H_0 (0x206C + DMA_REG_BASE)
/*Interrupt pending
register. high part. region 0*/
+
+#define DMA_ICR_0 (0x2070 + DMA_REG_BASE)
/*Interrupt clear
register. low pert. region 0*/
+#define DMA_ICR_H_0 (0x2074 + DMA_REG_BASE)
/*Interrupt clear
register. high part. region 0*/
+
+#define DMA_IER_0 (0x2050 + DMA_REG_BASE)
/*Interrupt enable.
low part. region 0*/
+#define DMA_IER_H_0 (0x2054 + DMA_REG_BASE)
/*Interrupt enable.
high part. region 0*/
+
+#define DMA_IESR_0 (0x2060 + DMA_REG_BASE)
/*Interrupt set
enable. low part. region 0*/
+#define DMA_IESR_H_0 (0x2064 + DMA_REG_BASE)
/*Interrupt set
enable. high part. region 0*/
+
+#define DMA_ESR_0 (0x2010 + DMA_REG_BASE)
/*Event set. low
part. region 0*/
+#define DMA_ESR_H_0 (0x2014 + DMA_REG_BASE)
/*Event set. high
part. region 0*/
+
+typedef struct _dma_regs_
+{
+ volatile unsigned int OPT;
+ volatile unsigned int SRC;
+ volatile unsigned int BCNT_ACNT;
+ volatile unsigned int DST;
+ volatile unsigned int DSTBIDX_SRCBIDX;
+ volatile unsigned int BCTNRDL_LINK;
+ volatile unsigned int DSTCIDX_SRCCIDX;
+ volatile unsigned int CCNT_Rsvd;
+} dmaRegs;
+
+#define DMA_PARAM_SET_N(n) ((dmaRegs*)PARAM_SET(n))
+
+#define DDR_MEM_BASE 0x80000000u
/* -------------------------------------------------------------------------- *
* AEMIF Register structure - See sprue20a.pdf for more details. *
diff -uNr uartapp/uartapp.c Quartapp/uartapp.c
--- uartapp/uartapp.c 2006-11-15 15:41:08.000000000 +0300
+++ Quartapp/uartapp.c 2008-01-24 15:58:56.000000000 +0300
@@ -66,6 +66,129 @@
return E_PASS;
}
+#define DMA_TO_ARM
+/*#define DMA_FROM_ARM*/
+
+#define SET_REGISTER(rg, vl) (*(unsigned int*)rg) = vl;
+
+unsigned int DMATest(void)
+{
+ const unsigned int value = 0x55AA55AA;
+ const unsigned int startPoint = 0;
+ const unsigned int startPoint2 = 1024;
+ const int size = 512;
+ const int set = 0; /*Number of PaRAM set*/
+
+ unsigned int res = E_PASS;
+ int i = 0, j = 0;
+ volatile unsigned int array[size];
+ volatile unsigned int array2[size];
+
+#ifdef DMA_FROM_ARM
+ for(i = 0; i < size; i++)
+ array[i] = value;
+#else
+ for(i = startPoint2; i < size + startPoint2; i++)
+ DDRMem[i] = value;
+#endif
+#ifdef DMA_TO_ARM
+ for(i = 0; i < size; i++)
+ array2[i] = 0;
+#else
+ for(i = startPoint; i < size + startPoint; i++)
+ DDRMem[i] = 0;
+#endif
+
+ UARTSendData("\r\nStarting DMA test. ");
+#ifdef DMA_TO_ARM
+ UARTSendData("To ARM ");
+#else
+ UARTSendData("To DDR2 ");
+#endif
+#ifdef DMA_FROM_ARM
+ UARTSendData("from ARM");
+#else
+ UARTSendData("from DDR2");
+#endif
+
+ // Enable interrupt
+ SET_REGISTER(DMA_IESR, 1 << set)
+
+ i = 10; while(i > 0){asm (" NOP");i--;}
+
+ // Set PaRAM
+ DMA_PARAM_SET_N(set)->OPT = 0x00100008u;
// Non static,
completion interrupt enabled
+ DMA_PARAM_SET_N(set)->BCNT_ACNT = 0x00010000u | size * 4; //
BCNT =
1; ACNT = size * 4
+ DMA_PARAM_SET_N(set)->BCTNRDL_LINK = 0xFFFFu;
// No link
+ DMA_PARAM_SET_N(set)->CCNT_Rsvd = 0x1u;
// CCNT = 1
+#ifdef DMA_FROM_ARM
+ DMA_PARAM_SET_N(set)->SRC = (unsigned int)array;
// Source
+#else
+ DMA_PARAM_SET_N(set)->SRC = DDR_MEM_BASE + startPoint2 * 4; //
Source
+#endif
+#ifdef DMA_TO_ARM
+ DMA_PARAM_SET_N(set)->DST = (unsigned int)array2;
// Destination
+#else
+ DMA_PARAM_SET_N(set)->DST = DDR_MEM_BASE + startPoint * 4; //
Destination
+#endif
+
+ i = 10; while(i > 0){asm (" NOP");i--;} /*without this it hangs*/
+
+ /* Start transfer*/
+ SET_REGISTER(DMA_ESR, 1 << set)
+
+ UARTSendData("\r\nEnter loop.");
+ while(!(*(unsigned int*)DMA_IPR))
+ {
+ asm (" NOP");
+ }
+
+ UARTSendData("\r\nError status = ");
+ UARTSendInt((*(unsigned int*)DMA_CCERR));
+ UARTSendData("\r\nMissed events = ");
+ UARTSendInt((*(unsigned int*)DMA_EMR));
+ UARTSendData("\r\nMissed events (H) = ");
+ UARTSendInt((*(unsigned int*)DMA_EMR_H));
+
+ UARTSendData("\r\nChecking...");
+#ifdef DMA_TO_ARM
+ for(i = 0; i < size; i++)
+ {
+ if(array2[i] != value)
+ {
+ UARTSendData("\r\nTest failed at ");
+ UARTSendInt((unsigned int)i);
+ UARTSendData(" value = ");
+ UARTSendInt(array2[i]);
+ res = E_FAIL;
+ if(array2[i] == 0)
+ {
+ UARTSendData("\r\nZero");
+ break;
+ }
+ }
+ }
+#else
+ for(i = startPoint, j = 0; i < size + startPoint; i++, j++)
+ {
+ if(DDRMem[i] != value)
+ {
+ UARTSendData("\r\nTest failed at ");
+ UARTSendInt((unsigned int)j);
+ UARTSendData(" value = ");
+ UARTSendInt(DDRMem[i]);
+ res = E_FAIL;
+ if(DDRMem[i] == 0)
+ {
+ UARTSendData("\r\nZero");
+ break;
+ }
+ }
+ }
+#endif
+ return res;
+}
+
void aemif_start()
{
asm (" NOP"); //needed to prevent compiler optimizing away
@@ -89,6 +212,7 @@
UARTSendData("\t1) Print Hello World!.\r\n");
UARTSendData("\t2) Initialize and test DDR RAM.\r\n");
UARTSendData("\t3) Boot out of NOR flash.\r\n");
+ UARTSendData("\t4) Test DMA.\r\n");
UARTSendData("\n\tEnter selection followed by <Enter>: ");
while (UARTRecvData(2,inData) != E_PASS);
@@ -107,6 +231,12 @@
case (3):
aemif_start();
break;
+ case (4):
+ if(DMATest() == E_PASS)
+ UARTSendData("\r\nDMA Test Passed");
+ else
+ UARTSendData("\r\nDMA Test Failed");
+ break;
default:
UARTSendData("\r\nInvalid Selection!\r\n");
break;
diff -uNr uartapp/uartapp.h Quartapp/uartapp.h
--- uartapp/uartapp.h 2006-11-15 15:41:10.000000000 +0300
+++ Quartapp/uartapp.h 2008-01-24 15:31:59.000000000 +0300
@@ -13,6 +13,7 @@
void aemif_start( void ) __attribute__((naked,section(".aemif")));
unsigned int DDRTest(void);
+unsigned int DMATest(void);
int uartapp_main( void );
------------------------------
Message: 2
Date: Thu, 24 Jan 2008 09:14:28 -0500
From: David A Kondrad <[EMAIL PROTECTED]>
Subject: Re: Capturing NTSC video (DVEM)
To: [EMAIL PROTECTED]
Cc: davinci-linux-open-source@linux.davincidsp.com
Message-ID:
<[EMAIL PROTECTED]>
Content-Type: text/plain; charset=US-ASCII
Rajen,
You can capture 720x240 (progressive 30 fps) on the Davinci by setting up
the V4L2 capture driver to throw away the even or odd frame interlaced
frame.
In the VIDIOC_S_FMT ioctl, change the v4l2_field struct member from
V4L2_FIELD_INTERLACED to either V4L2_FIELD_TOP or V4L2_FIELD_BOTTOM.
Here's the docs:
http://v4l2spec.bytesex.org/spec-single/v4l2.html#PIXFMT
http://v4l2spec.bytesex.org/spec-single/v4l2.html#VIDIOC-G-FMT
http://v4l2spec.bytesex.org/spec-single/v4l2.html#V4L2-FIELD
Hope that helps!
David
DAVID A. KONDRAD
Software Design Engineer
On-Q/Legrand
www.onqlegrand.com
------------------------------
Message: 3
Date: Thu, 24 Jan 2008 16:13:29 +0100
From: "Monk, Roger" <[EMAIL PROTECTED]>
Subject: RE: DMA transfer from ARM RAM
To: "Alexander Vasiliev" <[EMAIL PROTECTED]>,
<davinci-linux-open-source@linux.davincidsp.com>
Message-ID: <[EMAIL PROTECTED]>
Content-Type: text/plain; charset="us-ascii"
Forwarding for archive :-
Thanks Vasiliev - glad working ok now.
Cheers,
~roger
-----Original Message-----
From: Alexander Vasiliev [mailto:[EMAIL PROTECTED]
Sent: 24 January 2008 15:10
To: Monk, Roger
Subject: Re: DMA transfer from ARM RAM
Thank you, Roger.
Now it works well.
2008/1/24, Monk, Roger <[EMAIL PROTECTED]>:
Hi Vasiliev,
Can you try enabling the TCM memories (via ARM CP15) and let me know
please?
/* Set CP15 to enable the DTCM and ITCM */
static void enable_tcm_cp15 (void)
{
asm ("mov R0, #0x8\n"
"mov R0, R0, lsl #12 \n"
"orr R0, R0, #0x15\n"
"mcr p15, 0, R0, c9, c1, 0 \n"
"mov R0, #0x0000\n"
"orr R0, R0, #0x1\n"
"mcr p15, 0, R0, c9, c1, 1" : : );
return;
}
~roger
-----Original Message-----
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] On
Behalf Of Alexander Vasiliev
Sent: 24 January 2008 13:54
To: davinci-linux-open-source@linux.davincidsp.com
Subject: DMA transfer from ARM RAM
Hello,
I want to use EDMA during booting. So i am testing data transfer from
ARM RAM to DRR2. Copying from DRR to arm goes fine. But during copying
from arm to ddr2, every (29-31)th bytes are broken. Any ideas?
As the base application i use spraai0-application. Here is the patch
for
it:
diff -uNr uartapp/dm644x.h Quartapp/dm644x.h
--- uartapp/dm644x.h 2006-11-15 13:39:28.000000000 +0300
+++ Quartapp/dm644x.h 2008-01-24 15:33:09.000000000 +0300
@@ -180,6 +180,72 @@
#define DDR_TEST_PATTERN 0xA55AA55Au
#define DDR_RAM_SIZE 0x10000000u
+/*---------------------------------------------------------------------
-------
+DMA register structure
+-----------------------------------------------------------------------
-------*/
+
+#define DMA_REG_BASE 0x01C00000
/*base for dma registers*/
+
+#define PARAM_SET_BASE (DMA_REG_BASE + 0x4000)
/*base for PaRAM sets*/
+#define PARAM_SET_OFFSET 0x20
/*offset between PaRAM stes*/
+#define PARAM_SET(n) (PARAM_SET_BASE + n *
PARAM_SET_OFFSET)
/*PaRAM set n*/
+
+#define DMA_DRAE (0x0340 + DMA_REG_BASE)
/*Region access
enable. low part*/
+#define DMA_DRAE_H (0x0344 + DMA_REG_BASE)
/*Region access
enable*. high part*/
+
+#define DMA_IPR (0x1068 +
DMA_REG_BASE)
/*Interrupt pending
register. low part*/
+#define DMA_IPR_H (0x106C + DMA_REG_BASE)
/*Interrupt pending
register. high part*/
+
+#define DMA_EMR (0x0300 +
DMA_REG_BASE)
/*Event missed. low part*/
+#define DMA_EMR_H (0x0304 + DMA_REG_BASE)
/*Event missed. high part*/
+
+#define DMA_CCERR (0x0318 + DMA_REG_BASE)
/*Error*/
+
+#define DMA_SER (0x1038 +
DMA_REG_BASE)
/*Secondary event. low part*/
+#define DMA_SER_H (0x103C + DMA_REG_BASE)
/*Secondary event. high part*/
+
+#define DMA_SECR (0x1040 + DMA_REG_BASE)
/*Secondary event
clear. low part*/
+#define DMA_SECR_H (0x1044 + DMA_REG_BASE)
/*Secondary event
clear. high part*/
+
+#define DMA_ICR (0x1070 +
DMA_REG_BASE)
/*Interrupt clear
register. low pert*/
+#define DMA_ICR_H (0x1074 + DMA_REG_BASE)
/*Interrupt clear
register. high part*/
+
+#define DMA_IESR (0x1060 + DMA_REG_BASE)
/*Interrupt set
enable. low part*/
+#define DMA_IESR_H (0x1064 + DMA_REG_BASE)
/*Interrupt set
enable. high part*/
+
+#define DMA_ESR (0x1010 +
DMA_REG_BASE)
/*Event set. low part*/
+#define DMA_ESR_H (0x1014 + DMA_REG_BASE)
/*Event set. high part*/
+
+#define DMA_IPR_0 (0x2068 + DMA_REG_BASE)
/*Interrupt pending
register. low part. region 0*/
+#define DMA_IPR_H_0 (0x206C + DMA_REG_BASE)
/*Interrupt pending
register. high part. region 0*/
+
+#define DMA_ICR_0 (0x2070 + DMA_REG_BASE)
/*Interrupt clear
register. low pert. region 0*/
+#define DMA_ICR_H_0 (0x2074 + DMA_REG_BASE)
/*Interrupt clear
register. high part. region 0*/
+
+#define DMA_IER_0 (0x2050 + DMA_REG_BASE)
/*Interrupt enable.
low part. region 0*/
+#define DMA_IER_H_0 (0x2054 + DMA_REG_BASE)
/*Interrupt enable.
high part. region 0*/
+
+#define DMA_IESR_0 (0x2060 + DMA_REG_BASE)
/*Interrupt set
enable. low part. region 0*/
+#define DMA_IESR_H_0 (0x2064 + DMA_REG_BASE)
/*Interrupt set
enable. high part. region 0*/
+
+#define DMA_ESR_0 (0x2010 + DMA_REG_BASE)
/*Event set. low
part. region 0*/
+#define DMA_ESR_H_0 (0x2014 + DMA_REG_BASE)
/*Event set. high
part. region 0*/
+
+typedef struct _dma_regs_
+{
+ volatile unsigned int OPT;
+ volatile unsigned int SRC;
+ volatile unsigned int BCNT_ACNT;
+ volatile unsigned int DST;
+ volatile unsigned int DSTBIDX_SRCBIDX;
+ volatile unsigned int BCTNRDL_LINK;
+ volatile unsigned int DSTCIDX_SRCCIDX;
+ volatile unsigned int CCNT_Rsvd;
+} dmaRegs;
+
+#define DMA_PARAM_SET_N(n) ((dmaRegs*)PARAM_SET(n))
+
+#define DDR_MEM_BASE 0x80000000u
/*
------------------------------------------------------------------------
-- *
* AEMIF Register structure - See sprue20a.pdf for more details.
*
diff -uNr uartapp/uartapp.c Quartapp/uartapp.c
--- uartapp/uartapp.c 2006-11-15 15:41:08.000000000 +0300
+++ Quartapp/uartapp.c 2008-01-24 15:58:56.000000000 +0300
@@ -66,6 +66,129 @@
return E_PASS;
}
+#define DMA_TO_ARM
+/*#define DMA_FROM_ARM*/
+
+#define SET_REGISTER(rg, vl) (*(unsigned int*)rg) = vl;
+
+unsigned int DMATest(void)
+{
+ const unsigned int value = 0x55AA55AA;
+ const unsigned int startPoint = 0;
+ const unsigned int startPoint2 = 1024;
+ const int size = 512;
+ const int set = 0; /*Number of PaRAM set*/
+
+ unsigned int res = E_PASS;
+ int i = 0, j = 0;
+ volatile unsigned int array[size];
+ volatile unsigned int array2[size];
+
+#ifdef DMA_FROM_ARM
+ for(i = 0; i < size; i++)
+ array[i] = value;
+#else
+ for(i = startPoint2; i < size + startPoint2; i++)
+ DDRMem[i] = value;
+#endif
+#ifdef DMA_TO_ARM
+ for(i = 0; i < size; i++)
+ array2[i] = 0;
+#else
+ for(i = startPoint; i < size + startPoint; i++)
+ DDRMem[i] = 0;
+#endif
+
+ UARTSendData("\r\nStarting DMA test. ");
+#ifdef DMA_TO_ARM
+ UARTSendData("To ARM ");
+#else
+ UARTSendData("To DDR2 ");
+#endif
+#ifdef DMA_FROM_ARM
+ UARTSendData("from ARM");
+#else
+ UARTSendData("from DDR2");
+#endif
+
+ // Enable interrupt
+ SET_REGISTER(DMA_IESR, 1 << set)
+
+ i = 10; while(i > 0){asm (" NOP");i--;}
+
+ // Set PaRAM
+ DMA_PARAM_SET_N(set)->OPT = 0x00100008u;
// Non static,
completion interrupt enabled
+ DMA_PARAM_SET_N(set)->BCNT_ACNT = 0x00010000u | size * 4;
// BCNT =
1; ACNT = size * 4
+ DMA_PARAM_SET_N(set)->BCTNRDL_LINK = 0xFFFFu;
// No link
+ DMA_PARAM_SET_N(set)->CCNT_Rsvd = 0x1u;
// CCNT = 1
+#ifdef DMA_FROM_ARM
+ DMA_PARAM_SET_N(set)->SRC = (unsigned int)array;
// Source
+#else
+ DMA_PARAM_SET_N(set)->SRC = DDR_MEM_BASE + startPoint2 * 4;
// Source
+#endif
+#ifdef DMA_TO_ARM
+ DMA_PARAM_SET_N(set)->DST = (unsigned int)array2;
// Destination
+#else
+ DMA_PARAM_SET_N(set)->DST = DDR_MEM_BASE + startPoint * 4;
// Destination
+#endif
+
+ i = 10; while(i > 0){asm (" NOP");i--;} /*without this it
hangs*/
+
+ /* Start transfer*/
+ SET_REGISTER(DMA_ESR, 1 << set)
+
+ UARTSendData("\r\nEnter loop.");
+ while(!(*(unsigned int*)DMA_IPR))
+ {
+ asm (" NOP");
+ }
+
+ UARTSendData("\r\nError status = ");
+ UARTSendInt((*(unsigned int*)DMA_CCERR));
+ UARTSendData("\r\nMissed events = ");
+ UARTSendInt((*(unsigned int*)DMA_EMR));
+ UARTSendData("\r\nMissed events (H) = ");
+ UARTSendInt((*(unsigned int*)DMA_EMR_H));
+
+ UARTSendData("\r\nChecking...");
+#ifdef DMA_TO_ARM
+ for(i = 0; i < size; i++)
+ {
+ if(array2[i] != value)
+ {
+ UARTSendData("\r\nTest failed at ");
+ UARTSendInt((unsigned int)i);
+ UARTSendData(" value = ");
+ UARTSendInt(array2[i]);
+ res = E_FAIL;
+ if(array2[i] == 0)
+ {
+ UARTSendData("\r\nZero");
+ break;
+ }
+ }
+ }
+#else
+ for(i = startPoint, j = 0; i < size + startPoint; i++, j++)
+ {
+ if(DDRMem[i] != value)
+ {
+ UARTSendData("\r\nTest failed at ");
+ UARTSendInt((unsigned int)j);
+ UARTSendData(" value = ");
+ UARTSendInt(DDRMem[i]);
+ res = E_FAIL;
+ if(DDRMem[i] == 0)
+ {
+ UARTSendData("\r\nZero");
+ break;
+ }
+ }
+ }
+#endif
+ return res;
+}
+
void aemif_start()
{
asm (" NOP"); //needed to prevent compiler optimizing away
@@ -89,6 +212,7 @@
UARTSendData("\t1) Print Hello World!.\r\n");
UARTSendData("\t2) Initialize and test DDR RAM.\r\n");
UARTSendData("\t3) Boot out of NOR flash.\r\n");
+ UARTSendData("\t4) Test DMA.\r\n");
UARTSendData("\n\tEnter selection followed by <Enter>: ");
while (UARTRecvData(2,inData) != E_PASS);
@@ -107,6 +231,12 @@
case (3):
aemif_start();
break;
+ case (4):
+ if(DMATest() == E_PASS)
+ UARTSendData("\r\nDMA Test Passed");
+ else
+ UARTSendData("\r\nDMA Test Failed");
+ break;
default:
UARTSendData("\r\nInvalid Selection!\r\n");
break;
diff -uNr uartapp/uartapp.h Quartapp/uartapp.h
--- uartapp/uartapp.h 2006-11-15 15:41:10.000000000 +0300
+++ Quartapp/uartapp.h 2008-01-24 15:31:59.000000000 +0300
@@ -13,6 +13,7 @@
void aemif_start( void ) __attribute__((naked,section(".aemif")));
unsigned int DDRTest(void);
+unsigned int DMATest(void);
int uartapp_main( void );
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------------------------------
Message: 4
Date: Thu, 24 Jan 2008 11:58:29 -0600
From: "Ring, Chris" <[EMAIL PROTECTED]>
Subject: RE: How to make CMEM cacheable on ARM side on DM6446?
To: "Kumar Brajbhushan" <[EMAIL PROTECTED]>,
<davinci-linux-open-source@linux.davincidsp.com>
Message-ID:
<[EMAIL PROTECTED]>
Content-Type: text/plain; charset="us-ascii"
Glad to hear that worked for you - not too many users of that feature
just yet!
Detailed replies inlined below...
Chris
-----Original Message-----
From: Kumar Brajbhushan [mailto:[EMAIL PROTECTED]
Sent: Wednesday, January 23, 2008 11:15 PM
To: Ring, Chris; davinci-linux-open-source@linux.davincidsp.com
Subject: RE: How to make CMEM cacheable on ARM side on DM6446?
Chris,
Thanks again. It does work. :)
Is it possible to associate this setting at algorithm level only? That
is algo "A" has cache enabled and "B" does not and both run
in the same
process.
No. Today, it's a "global", per-app setting. That is, your executable
has this setting built into its binary executable image, and all 'local'
algs created by that app will use that setting.
How do you associate this setting with any particular process? Please
elaborate.
As mentioned, the setting is per-app. If you build app1 with ".useCache
= true", and you build app2 with ".useCache = false", they'll request
the memory for the codecs differently.
I had some more queries in previous mail. I will wait for
their answers.
Do you imply that CMEM is used for algorithm creation ONLY
when it is
local? I was under the impression that CMEM has to be used
for remote
components (DSP-side).
In general, when an app issues a *_create() call, the ti.sdo.ce.alg
package is used to grant memory to the algorithms. This ti.sdo.ce.alg
package is built into both the ARM and DSP side executables (App and
Server). In particular, in CE 2.00:
* Algs on ARM-based systems get memory via CMEM.
* Algs on DSP/BIOS-based systems get memory via DSKT2 (which
ultimately uses BIOS).
* Algs on x86-based systems get memory via malloc().
[ FYI, the above holds for CE releases prior to CE 2.00 _except_
ARM-based algs used to get memory from malloc(). We switched from
malloc() to CMEM when we realized ARM-side algs want to use HW
accelerators, and those accelerators needed physically contiguous memory
as well! ]
To restate, when the ARM-side app creates a 'local' alg, the
ti.sdo.ce.alg requests memory from CMEM to satisfy the alg requests. If
the ARM-side app creates a 'remote' alg, the _Server-side_ ti.sdo.ce.alg
requests memory from DSKT2/BIOS to satisfy the alg requests.
[ For completeness, on DM355, there are only 'local' ARM-side algs, so
all alg memory comes from CMEM. On DM6437, there are only 'local'
DSP-side algs, so all alg memory comes from DSKT2/BIOS. ]
Perhaps the confusion is that CMEM is _also_ used to allocate the app
data buffers (via Memory_allocContig()). It is true that _data_ buffers
bound for the DSP must be physically contiguous, and CMEM is typically
used for this. But again, these _app_ data buffers are different than
the _alg_ memory we're discussing.
One related query is how does CE support memory relocation? Is it
possible for application to override the memory allocated
by CE for an
algorithm on ARM-side or DSP-side?
Today, no. The alg buffers are provide by the ti.sdo.ce.alg package,
and there are no hooks for other allocators. For ARM-side algs, there
is some app-level configurability (e.g. the .useCache and .useHeap
config params), and for DSP-side algs there is even more
DSKT2/BIOS-based configurability. But currently the application cannot
supply arbitrary buffers to satisfy the alg's IALG-based, memTab
requests.
Best Regards,
Kumar
-----Original Message-----
From: Ring, Chris [mailto:[EMAIL PROTECTED]
Sent: Thursday, January 24, 2008 11:35 AM
To: Kumar Brajbhushan; davinci-linux-open-source@linux.davincidsp.com
Subject: RE: How to make CMEM cacheable on ARM side on DM6446?
There is a config param in the new ti.sdo.ce.alg.Settings module, very
poorly documented in CE 2.00, but we'll have better docs in future
releases. The config param you care about is .useCache, by
default it's
false, but you can set it to true in your app's .cfg script.
Something
like:
algSettings = xdc.useModule('ti.sdo.ce.alg.Settings');
algSettings.useCache = true;
Once you set .useCache to true, all memory provided to the
ARM-side algs
will have its cache enabled - this is an app-wide flag.
(Interestingly,
apps in other processes can set this flag differently if they wish!)
[ For those following along, note that this memory is memory the _alg_
requests under the covers during the *_create() calls. We're not
talking about the data buffers which the _app_ requests. _Those_ app
buffers can also now be requested to be cached on a per-buffer basis,
using the 'params' field of the new Memory_alloc() fxn, in CE 2.00. ]
And finally, I'm not sure whether you'll stumble on any cache-related
coherency issues in your codec - if all references to that memory are
via the CPU, you should be fine.
Hope that helps!
Chris
-----Original Message-----
From: Kumar Brajbhushan [mailto:[EMAIL PROTECTED]
Sent: Wednesday, January 23, 2008 8:24 PM
To: Ring, Chris; davinci-linux-open-source@linux.davincidsp.com
Subject: RE: How to make CMEM cacheable on ARM side on DM6446?
Chris,
Thanks a lot!
I am using CE 2.0, XDC_3_00_2, bios_5_31_08 for a non-VISA
component. I
have written stubs/skeletons for this component based on example one
available for video component. Yes, I am trying to run the component
from ARM side as local.
As compared to the case when the component is run without
Codec Engine,
it takes 11 times more time for execution. I found the
culprit to be the
memories allocated by Memory_contigAlloc() and VISA_create.
The allocate
memories in CMEM. Instead if I override those memory chunks with one
allocated on heap (ARM-side) via malloc() then there is no
performance
penalty. That's the reason I am looking for an option to make CMEM
cacheable on ARM-side.
Do you imply that CMEM is used for algorithm creation ONLY
when it is
local? I was under the impression that CMEM has to be used
for remote
components (DSP-side).
One related query is how does CE support memory relocation? Is it
possible for application to override the memory allocated
by CE for an
algorithm on ARM-side or DSP-side?
Best Regards,
Kumar
-----Original Message-----
From: Ring, Chris [mailto:[EMAIL PROTECTED]
Sent: Wednesday, January 23, 2008 10:35 PM
To: Kumar Brajbhushan;
davinci-linux-open-source@linux.davincidsp.com
Subject: RE: How to make CMEM cacheable on ARM side on DM6446?
Can you help us understand your usage a little better (and
which version
of CE you're using)?
VISA_create() is an "SPI" - System Programming Interface - used by
algorithm providers that are integrating non-xDM algorithms into the
Codec Engine environment. Is that what you're trying to do?
And CMEM is only used during algorithm creation when the
alg is local
(i.e. ARM-side). Is that also what you're trying to do?
[ And finally, just to tempt you, the recently released CE
2.00 and CMEM
2.00 have some cache-able buffer support... I just want to
understand
your use case before making a recommendation. ]
Chris
-----Original Message-----
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED]
] On Behalf Of Kumar Brajbhushan
Sent: Wednesday, January 23, 2008 2:48 AM
To: davinci-linux-open-source@linux.davincidsp.com
Subject: How to make CMEM cacheable on ARM side on DM6446?
All,
I am trying to profile a component on ARM side of DM6446.
VISA_Create
allocates memory for this component from CMEM area which is
not cached
on ARM side. Because of this there is huge increase in the
time taken
for processing.
Is there a way to cache this CMEM on ARM side as well? Or
to direct
VISA_create to allocate memories from other sections
(non-CMEM, memory
cached on ARM side).
Best Regards,
Kumar
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