Hi,

Sorry about replying to my own email but I only get the digests.

On Wed, May 19, 2010 at 5:38 PM, Juha Kuikka <juha.kui...@gmail.com> wrote:
>
> I am working with a HW that has an SDIO device on the second
> MMC/SD/SDIO controller (mmcsd1).
>
> I suspect the DMA channel numbers are wrong or for some reason the
> second EDMA controller has issues.
>

Turns out the issue is the EDMA configuration.

DA850 has two EDMA controllers. Unfortunately they are not identical,
the first instance has two transfer controllers and two event queues
but the second instance only has one of each.

The static int __init edma_probe(struct platform_device *pdev)
-function in dma.c has this code in it:

                edma_info[j]->default_queue = info[j].default_queue;
                if (!edma_info[j]->default_queue)
                        edma_info[j]->default_queue = EVENTQ_1;

                /* Everything lives on transfer controller 1 until otherwise
                 * specified. This way, long transfers on the low priority queue
                 * started by the codec engine will not cause audio defects.
                 */
                for (i = 0; i < edma_info[j]->num_channels; i++)
                        map_dmach_queue(j, i, EVENTQ_1);

And because the MMC driver allocates channels with EVENTQ_DEFAULT they
get put into EVENTQ_1 which the second EDMA controller does not have
and hence transfers stall.

My proposal for a fix would be something like this:

--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -186,6 +186,7 @@ static struct edma_soc_info da850_edma_info[] = {
                .n_cc                   = 1,
                .queue_tc_mapping       = da8xx_queue_tc_mapping,
                .queue_priority_mapping = da8xx_queue_priority_mapping,
+               .default_queue          = EVENTQ_1,
        },
        {
                .n_channel              = 32,
@@ -195,6 +196,7 @@ static struct edma_soc_info da850_edma_info[] = {
                .n_cc                   = 1,
                .queue_tc_mapping       = da850_queue_tc_mapping,
                .queue_priority_mapping = da850_queue_priority_mapping,
+               .default_queue          = EVENTQ_0,
        },
 };

--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -1447,8 +1447,6 @@ static int __init edma_probe(struct platform_device *pdev)
                                                        EDMA_MAX_CC);

                edma_info[j]->default_queue = info[j].default_queue;
-               if (!edma_info[j]->default_queue)
-                       edma_info[j]->default_queue = EVENTQ_1;

                dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
                        edmacc_regs_base[j]);
@@ -1508,7 +1506,7 @@ static int __init edma_probe(struct platform_device *pdev)
                 * started by the codec engine will not cause audio defects.
                 */
                for (i = 0; i < edma_info[j]->num_channels; i++)
-                       map_dmach_queue(j, i, EVENTQ_1);
+                       map_dmach_queue(j, i, edma_info[j]->default_queue);

                queue_tc_mapping = info[j].queue_tc_mapping;
                queue_priority_mapping = info[j].queue_priority_mapping;

Comments?

 / Juha
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