Hi, I am working with the OMAP-L138 and I think there may be a problem with the 456 MHz OPP point and using the EMIFA. The EMIFA max clock rate is specified at 148 MHz. By default, the EMIFA is driven by PLL0_SYSCLK3 (or 1/3 the CPU rate).
At 456 MHz, this is 152 MHz. In addition to being out of spec, it looks like the aemif code that sets up wait state divisor settings is getting called by the MTD/NAND probe() code at startup, but doesn't register and recompute the timings if someone starts messing with the OPP (e.g., cranks it up from 300 MHz to 456 MHz) and the affected clock. There is a 4.5 divisor option (versus using PLL0_SYSCLK3) which would bring the timing back into specification at 456 MHz, but I am not sure where to plumb this code in, and when to call it. It seems application specific for OPPs below 456 MHz, and a requirement for the 456 MHz OPP. Would a sysfs attribute be appropriate? It would also seem that the NAND driver should register for clk change notification and update the CE space timings on change. I don't know if this is an issue with the DA830 / OMAP-L137, I am not familiar with the part. -Mike _______________________________________________ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
