On Tue, Dec 17, 2013 at 3:10 PM, Toru Nishimura <tslee...@gmail.com> wrote: >> First let me tell you that having this kind of discussion is really helping >> and no-one >> (I hope) is getting angry about it here. > > Thank you Yann. I'm a person who love to study about the efforts made by > senior > engineers in human civilization. Here is a good reading for such a > kind of person > to extend knowledge about MMU and TLB. > > http://www.broadcom.com/collateral/wp/SB-1_WP100-R.pdf >
That's indeed a well written document, thanks for sharing! You might however question the objectiveness of it, being a whitepaper from a company guiding people to switch from PowerPC to their MIPS chip. ;) I don't think it was bad in that regard though. > It's lengthy and takes time to finish reading. Pages I would emphasis on; > > Page-2; "it helps to understand the problems that the architects were > trying to solve." > Page-3; "it means that even a small system must program the MMUs on the > PowerPC > if it wishes to control ..." > "PowerPC turn off the MMUs when an exception occurs. But this also shuts down > the behavior control over memory (and I/O device registers to manipulate). > "To survive this, the interrupt service routine must reactivate > (immediately) MMUs, ..." > "There is no clean way to have exception occur ourside the translation > mechanism." > Ok, let's take a look at what the author is speaking about in the text you quoted. He's explaining that the PowerPC need to have the MMU turned on to control whether certain memory addresses are cached or non-cached. And he goes on explaining that this is a drawback in an embedded environment. That's all fine and something we all can agree on, but I'd like to add two comments to that. 1) I thought we we're discussing drawbacks on "large" OS's that utilize virtual memory, not embedded systems that *don't* need virtual memory. 2) LM32 doesn't work like PowerPC in that regard. Non-cached address spaces are configured at synthesis time (i.e. when you are designing the SoC), so you can access IO without the need to configure the MMU (or enable it at all for that matter). Stefan _______________________________________________ Devel mailing list Devel@lists.milkymist.org https://ssl.serverraum.org/lists/listinfo/devel
