Le 2014-01-09 22:28, Salman Sheikh a écrit :
I am trying to compile the lm32 testbench which I got from here
https://github.com/m-labs/lm32/tree/master/rtl [1]
with the Modelsim verilog compiler (vsim) and all files compiled
except this lm32_itlb.v
I got a complaint about the variable flushing. I see a flush input but
none for flushing.
Perhaps it only works in iverilog...
vlog +incdir+../rtl ../rtl/lm32_itlb.v
Model Technology ModelSim PE vlog 10.1b Compiler 2012.04 Apr 27 2012
-- Compiling module lm32_itlb
** Error: ../rtl/lm32_itlb.v(194): (vlog-2730) Undefined variable:
'flushing'.
Any clues why
--
Even a Smile is charity :)
- Prophet Muhammad
Links:
------
[1] https://github.com/m-labs/lm32/tree/master/rtl
Hello,
Thanks for reporting this issue :)
Indeed it's a problem, you need to add in lm32_itlb.v a "wire flushing;"
line somewhere.
In iverilog, it works, because iverilog assumes that any non declared
variable is a one bit wire.
It seems Modelsim does not do the same :)
I will propose a patch soon for that to commit on the github repository.
In the mean time please try with adding the previously mentioned line
Best regards,
Yann Sionneau
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