Hi guys: Any comments on the following list of key MiGen features? (additions? subtractions?)
- use Python as a high-level hardware description language - traditional synthesiser for converting Python (HDL) code into synthesizable HDL code (Verilog) - dataflow programming system - soc bus infrastructure (wishbone,CSR-R,LASMI,DFI) - simulator that allows test-benches to be written in Python - online training access (EDA Playground) - support for custom hardware platforms (RHINO, ROACH, Zedboard, Papillio etc) - direct interface with third-party FPGA design tools (using mibuild package) I will be giving a short presentation this friday at the "*High Performance Signal and Data Processing Workshop*"[1] - I plan to say something about MiGen and its current capabilities.Particularly, examining it as a potential tool for high-level design of SDR waveforms on FPGA platforms. [1] http://www.hpspsa.com/ Kind regards -- Khobatha Setetemela *Software Defined Radio Group (SDRG)* *University of Cape Townphone(cell): 0725239593phone(office): 021-650-3756* *skype: oksetetemela* *twitter: @khobatha* *"But seek ye first the kingdom of God, and His righteousness; and all these things shall be added unto you" (Matt 6:33)*
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