On Wed, Sep 22, 2010 at 11:51:11AM +0100, Mark Brown wrote: > On Wed, Sep 22, 2010 at 12:08:17AM -0300, Grant Likely wrote:
> > What's the irq handling latency on those? Glad I haven't had to deal > > with any of them yet. > Milisecondish, but depends on bus congestion and bus type. You need to > schedule a thread which then does one but typically more register I/O > operations on the device (read one or more IRQ status registers, and > typically write back to acknowledge the interrupts as well). These tend > for obvious reasons to be for low volume interrupts like jack detection. Incidentally, if you want to look at an implementation the wm831x contains an implementation of such a controller (in drivers/mfd/wm831x-irq.c) the structure of which has been cloned for quite a few of these chips. _______________________________________________ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss