From: Zhao Yakui <[email protected]>

Sometimes we will get the incorrect display modeline when parsing the detailed
timing in EDID. For example: 
   >hsync/vsync width is zero
   >sync is beyond the blank.

So add the basic check for the detailed timing in EDID to avoid the incorrect
display modeline. 

Signed-off-by: Zhao Yakui <[email protected]>
---
 drivers/gpu/drm/drm_edid.c |   15 +++++++++++++++
 1 file changed, 15 insertions(+)

Index: linux-2.6/drivers/gpu/drm/drm_edid.c
===================================================================
--- linux-2.6.orig/drivers/gpu/drm/drm_edid.c   2009-10-12 08:45:12.000000000 
+0800
+++ linux-2.6/drivers/gpu/drm/drm_edid.c        2009-10-14 09:08:10.000000000 
+0800
@@ -626,6 +626,12 @@
                return NULL;
        }
 
+       /* it is incorrect if hsync/vsync width is zero */
+       if (!hsync_pulse_width || !vsync_pulse_width) {
+               DRM_DEBUG_KMS("Incorrect Detailed timing. "
+                               "Wrong Hsync/Vsync pulse width\n");
+               return NULL;
+       }
        mode = drm_mode_create(dev);
        if (!mode)
                return NULL;
@@ -647,6 +653,15 @@
        mode->vsync_end = mode->vsync_start + vsync_pulse_width;
        mode->vtotal = mode->vdisplay + vblank;
 
+       /* perform the basic check for the detailed timing */
+       if (mode->hsync_end > mode->htotal ||
+               mode->vsync_end > mode->vtotal) {
+               drm_mode_destroy(dev, mode);
+               DRM_DEBUG_KMS("Incorrect detailed timing. "
+                               "Sync is beyond the blank.\n");
+               return NULL;
+       }
+
        drm_mode_set_name(mode);
 
        if (pt->misc & DRM_EDID_PT_INTERLACED)

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