I've got a make question I'm hoping someone can help me with.
I have three Makefiles
Makefile.a
Makefile.b
and Makefile
Makefile contains all the real targets and the .a and .b files simply export
a couple of variables and include Makefile. I want to eliminate Makefile.a
and Makefile.b by performing those exports dynamically based on the chosen
target, so "make mytargeta" would replace "make -f Makefile.a mytarget" and
"make mytargetb" would replace "make -f Makefile.b mytarget"
correspondingly. I can easily mimic this with a shell script sitting in
front of the Makefile, but I'd like to do it using only make if possible.
I'm coming to the conclusion that there's no provision in make for this.
The targets are inherited and fairly complex with multiple levels of
inclusion, so just rewriting all the makefiles is out of the question. Any
suggestions? I may just have to create a "build.sh" which matches the
target given as an argument and invokes make with the correct -f option.
-Mike
--
Science is the belief in the ignorance of experts. -- Richard Feynman
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