At 02:05 AM 5/22/2006, Peter Martinez wrote:
> >From G3PLX:
>
>
>Jim's point about poor (or missing) DC coupling probably crossed with my
>answer to Frank. It really is not a problem. Jim mentioned clock noise
>again, and I have to say I haven't studied this at all, but my understanding
>is that it is a strong-signal effect, not a noise level one. I don't think I
>have seen any such effects, but I haven't looked for them either.

Clock noise comes from a variety of sources, but imperfect power supply 
rejection is one case (that is, the A/D clock generator puts some amount of 
ripple on the power supply, which then couples into the signal path).  In 
any case, noise at the sampling rate aliases right to DC.   You see it with 
no input signal.  The tricky thing is if the noise isn't perfectly narrow 
band, because then it spreads out a bit. Otherwise, you could just take it 
out like any other DC bias.

Depending on how the circuit that makes the A/D clock frequency works, you 
can also get other noise components harmonically related to the sample 
rate, most of which will alias to either DC or to fs/2.

I would imagine that there's other sampling/mixing artifacts (i.e. leakage 
of the signals going to the QSD) that might manifest themselves at DC, but 
in a frequency dependent way (i.e. the I/Q imbalance or the skew between 
the mux control signals isn't symmetric).

Jim 



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