On 15 Oct 2017 Florian Klämpfl wrote: > I had a look and tested it and it worked, I didn't notice the problem below > either.
Sorry for wrong warning. I cannot provide any example where my suggestions are true. The reason for it is described on page Vol. 1 3-13 of Intel 64 and IA-32 Architectures Software Developer's Manual: > When in 64-bit mode, operand size determines the number of valid bits in > the destination general-purpose register: > > [...] > > 32-bit operands generate a 32-bit result, zero-extended to a 64-bit > result in the destination general-purpose > > [...] So, instructions > movzbl (%rcx),%eax and > movzbl -1(%rdx),%ecx and > xorl %eax,%eax should put zero into 32 high bits of appropriate registers. > I think also the final xor should be a xorq %rax,%rax, right? As I said above xorl %eax, %eax should be enough. -- With best regards Sergey _______________________________________________ fpc-devel maillist - fpc-devel@lists.freepascal.org http://lists.freepascal.org/cgi-bin/mailman/listinfo/fpc-devel
