------- Additional Comments From schlie at comcast dot net 2005-03-03 19:47 ------- (In reply to comment #6) Nope, these are peripheral i/o registers, and like any pheripheral interface may have access sequence requirements which need to be satsifyed within it's driver. These perpheral register's access sequence requirements have nothing to do with the avr's ISA or impled compiler requirments, just simply the conventions which need to be followed when attempting to access manipulate dynamically active 16-bit counter values through a pair of 8-bit i/o registers (which happen to be mapped in data address space, which isn't an uncommon, but implies nothing otherwise, other than you shouldn't assume that the compiler need sequence indirect access to arbitrary multi-word/byte transactions data to satisfy a peripheral's interface sequence that's the job of the author of the it's interface driver to guarantee; and by the way, you still need to disable interrupts if an interrupt routine may access the same registers, as all the sequence does is read/write upper 8-bit latched value when ever the lower 8-bit value is accessed, so therefore if you write the high value, get an interupt which writes both, then write the low value, you get the interrupt routines high value, combined with your new low value written, which isn't likely what you want.
-- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=20288
