------- Comment #7 from zadeck at naturalbridge dot com 2009-01-29 14:38 ------- Subject: Re: [4.3/4.4 Regression] life passes dump option still documented
Richard Guenther wrote: > On Wed, Jan 28, 2009 at 5:03 PM, Kenneth Zadeck > <zad...@naturalbridge.com> wrote: > >> rguenth at gcc dot gnu dot org wrote: >> >>> ------- Comment #3 from rguenth at gcc dot gnu dot org 2009-01-24 10:20 >>> ------- >>> GCC 4.3.3 is being released, adjusting target milestone. >>> >>> >>> >>> >> This may be more a change than is acceptable right now for 4.4. If so >> I will sit on this patch until 4.5 opens up. The patch is basically a >> complete rewrite of the part of invoke.texi that deals with dump options >> for the rtl pass. This section had badly rotted. >> >> I started from a grep of the sources looking for "rtl_opt_pass" and >> documented all of the passes that i found in mostly alphabetical >> order. Where the old version documented several passes together, I >> kept that unless things had changed. In total there were about a half >> dozen passes that were no longer there and about a dozen new passes that >> had not been documented. >> >> I did make some changes in the code, which is the reason that this may >> not be acceptable to 4.4. The changes are pretty harmless: all of them >> involve either removing the pass name or changing it. >> >> 1) Pass names that contained dashes had the dashes changed to >> underscores. About half used slashes and half underscores and I went >> with underscores to avoid a possible ambiguity with the options parsing. >> >> 2) I also removed the pass name from 6 passes that do not print anything >> or dump the code. >> > > I think this change is agains what was asked for in the past. We want to have > pass names for all passes. > > >> 3) Files that contained multiple passes with names of the form xx, >> xx2... were renamed xx1,xx2. >> This later change causes a test suit failure which was fixed. >> >> All of these changes are pretty minor. The only possible failure these >> can cause are in the test suite where dump files are scanned. >> >> I tested this on x86 and ppc both 32 and 64. It is possible that there >> are platform specific regression tests that scan for dump files that >> were not caught on these four targets. >> >> I also left in lreg and greg. These are at the end and need to be >> deleted along with those passes. >> >> I have enclosed a copy of the new text. The diff is unreadable. >> >> ok for 4.4 or should i wait for 4.5? >> > > This is ok for 4.4 if you remove the parts that remove pass names. Please > wait a day for comments from others. > > Thanks, > Richard. > > > I put those pass names back, but I documented them as producing no output. I also removed the lreg and greg part since the RA removal patch has been approved. committed as revision 143756 kenny 2009-01-29 Kenneth Zadeck <zad...@naturalbridge.com> PR middle-end/35854 * doc/invoke.texi (rtl debug options): Complete rewrite. * auto-inc-dec.c (pass_inc_dec): Rename pass from "auto-inc-dec" to auto_inc_dec". * mode-switching.c (pass_mode_switching): Rename pass from "mode-sw" to "mode_sw". * except.c (pass_convert_to_eh_ranges): Rename pass from "eh-ranges" to "eh_ranges". * lower-subreg.c (pass_lower_subreg): Renamed pass from "subreg" to "subreg1". 2009-01-29 Kenneth Zadeck <zad...@naturalbridge.com> PR middle-end/35854 * gcc.dg/lower-subreg-1.c: Renamed dump pass from "subreg" to "subreg1" Index: doc/invoke.texi =================================================================== --- doc/invoke.texi (revision 143754) +++ doc/invoke.texi (working copy) @@ -4545,172 +4545,275 @@ preprocessing. Debug dumps can be enabled with a @option{-fdump-rtl} switch or some @option{-d} option @var{letters}. Here are the possible -letters for use in @var{letters} and @var{pass}, and their meanings: +letters for use in @var{pass} and @var{letters}, and their meanings: @table @gcctabopt -...@item -dA -...@opindex dA -Annotate the assembler output with miscellaneous debugging information. + +...@item -fdump-rtl-alignments +...@opindex fdump-rtl-alignments +Dump after branch alignments have been computed. + +...@item -fdump-rtl-asmcons +...@opindex fdump-rtl-asmcons +Dump after fixing rtl statements that have unsatisfied in/out constraints. + +...@item -fdump-rtl-auto_inc_dec +...@opindex fdump-rtl-auto_inc_dec +Dump after auto-inc-dec discovery. This pass is only run on +architectures that have auto inc or auto dec instructions. + +...@item -fdump-rtl-barriers +...@opindex fdump-rtl-barriers +Dump after cleaning up the barrier instructions. + +...@item -fdump-rtl-bbpart +...@opindex fdump-rtl-bbpart +Dump after partitioning hot and cold basic blocks. @item -fdump-rtl-bbro @opindex fdump-rtl-bbro -Dump after block reordering, to @fi...@var{file}.148r.bbro}. +Dump after block reordering. + +...@item -fdump-rtl-btl1 +...@itemx -fdump-rtl-btl2 +...@opindex fdump-rtl-btl2 +...@opindex fdump-rtl-btl2 +...@option{-fdump-rtl-btl1} and @option{-fdump-rtl-btl2} enable dumping +after the two branch +target load optimization passes. + +...@item -fdump-rtl-bypass +...@opindex fdump-rtl-bypass +Dump after jump bypassing and control flow optimizations. @item -fdump-rtl-combine @opindex fdump-rtl-combine -Dump after the RTL instruction combination pass, to the file -...@file{@var{file}.129r.combine}. +Dump after the RTL instruction combination pass. + +...@item -fdump-rtl-compgotos +...@opindex fdump-rtl-compgotos +Dump after dumplicating the computed gotos. @item -fdump-rtl-ce1 @itemx -fdump-rtl-ce2 +...@itemx -fdump-rtl-ce3 @opindex fdump-rtl-ce1 @opindex fdump-rtl-ce2 -...@option{-fdump-rtl-ce1} enable dumping after the -first if conversion, to the file @fi...@var{file}.117r.ce1}. -...@option{-fdump-rtl-ce2} enable dumping after the second if -conversion, to the file @fi...@var{file}.130r.ce2}. +...@opindex fdump-rtl-ce3 +...@option{-fdump-rtl-ce1}, @option{-fdump-rtl-ce2}, and +...@option{-fdump-rtl-ce3} enable dumping after the three +if conversion passes. + +...@itemx -fdump-rtl-cprop_hardreg +...@opindex fdump-rtl-cprop_hardreg +Dump after hard register copy propagation. + +...@itemx -fdump-rtl-csa +...@opindex fdump-rtl-csa +Dump after combining stack adjustments. + +...@item -fdump-rtl-cse1 +...@itemx -fdump-rtl-cse2 +...@opindex fdump-rtl-cse1 +...@opindex fdump-rtl-cse2 +...@option{-fdump-rtl-cse1} and @option{-fdump-rtl-cse2} enable dumping after +the two common sub-expression elimination passes. + +...@itemx -fdump-rtl-dce +...@opindex fdump-rtl-dce +Dump after the standalone dead code elimination passes. -...@item -fdump-rtl-btl @itemx -fdump-rtl-dbr -...@opindex fdump-rtl-btl @opindex fdump-rtl-dbr -...@option{-fdump-rtl-btl} enable dumping after branch -target load optimization, to @fi...@var{file}.31.btl}. -...@option{-fdump-rtl-dbr} enable dumping after delayed branch -scheduling, to @fi...@var{file}.36.dbr}. - -...@item -dD -...@opindex dD -Dump all macro definitions, at the end of preprocessing, in addition to -normal output. - -...@item -fdump-rtl-ce3 -...@opindex fdump-rtl-ce3 -Dump after the third if conversion, to @fi...@var{file}.146r.ce3}. +Dump after delayed branch scheduling. -...@item -fdump-rtl-cfg -...@itemx -fdump-rtl-life -...@opindex fdump-rtl-cfg -...@opindex fdump-rtl-life -...@option{-fdump-rtl-cfg} enable dumping after control -and data flow analysis, to @fi...@var{file}.116r.cfg}. -...@option{-fdump-rtl-cfg} enable dumping dump after life analysis, -to @fi...@var{file}.128r.life1} and @fi...@var{file}.135r.life2}. - -...@item -fdump-rtl-greg -...@opindex fdump-rtl-greg -Dump after global register allocation, to @fi...@var{file}.139r.greg}. - -...@item -fdump-rtl-gcse -...@itemx -fdump-rtl-bypass -...@opindex fdump-rtl-gcse -...@opindex fdump-rtl-bypass -...@option{-fdump-rtl-gcse} enable dumping after GCSE, to -...@file{@var{file}.114r.gcse}. @option{-fdump-rtl-bypass} -enable dumping after jump bypassing and control flow optimizations, to -...@file{@var{file}.115r.bypass}. +...@item -fdump-rtl-dce1 +...@itemx -fdump-rtl-dce2 +...@opindex fdump-rtl-dce1 +...@opindex fdump-rtl-dce2 +...@option{-fdump-rtl-dce1} and @option{-fdump-rtl-dce2} enable dumping after +the two dead store elimination passes. @item -fdump-rtl-eh @opindex fdump-rtl-eh -Dump after finalization of EH handling code, to @fi...@var{file}.02.eh}. +Dump after finalization of EH handling code. -...@item -fdump-rtl-sibling -...@opindex fdump-rtl-sibling -Dump after sibling call optimizations, to @fi...@var{file}.106r.sibling}. +...@item -fdump-rtl-eh_ranges +...@opindex fdump-rtl-eh_ranges +Dump after conversion of EH handling range regions. -...@item -fdump-rtl-jump -...@opindex fdump-rtl-jump -Dump after the first jump optimization, to @fi...@var{file}.112r.jump}. +...@item -fdump-rtl-expand +...@opindex fdump-rtl-expand +Dump after RTL generation. -...@item -fdump-rtl-stack -...@opindex fdump-rtl-stack -Dump after conversion from GCC's "flat register file" registers to the -x87's stack-like registers, to @fi...@var{file}.152r.stack}. +...@item -fdump-rtl-fwprop1 +...@itemx -fdump-rtl-fwprop2 +...@opindex fdump-rtl-fwprop1 +...@opindex fdump-rtl-fwprop2 +...@option{-fdump-rtl-fwprop1} and @option{-fdump-rtl-fwprop2} enable +dumping after the two forward propagation passes. + +...@item -fdump-rtl-gcse1 +...@itemx -fdump-rtl-gcse2 +...@opindex fdump-rtl-gcse1 +...@opindex fdump-rtl-gcse2 +...@option{-fdump-rtl-gcse1} and @option{-fdump-rtl-gcse2} enable dumping +after global common subexpression elimination. + +...@item -fdump-rtl-init-regs +...@opindex fdump-rtl-init-regs +Dump after the initialization of the registers. + +...@item -fdump-rtl-initvals +...@opindex fdump-rtl-initvals +Dump after the computation of the initial value sets. + +...@itemx -fdump-rtl-into_cfglayout +...@opindex fdump-rtl-into_cfglayout +Dump after converting to cfglayout mode. + +...@item -fdump-rtl-ira +...@opindex fdump-rtl-ira +Dump after iterated register allocation. -...@item -fdump-rtl-lreg -...@opindex fdump-rtl-lreg -Dump after local register allocation, to @fi...@var{file}.138r.lreg}. +...@item -fdump-rtl-jump +...@opindex fdump-rtl-jump +Dump after the second jump optimization. @item -fdump-rtl-loop2 @opindex fdump-rtl-loop2 -...@option{-fdump-rtl-loop2} enables dumping after the -loop optimization pass, to @fi...@var{file}.119r.loop2}, -...@file{@var{file}.120r.loop2_init}, -...@file{@var{file}.121r.loop2_invariant}, and -...@file{@var{file}.125r.loop2_done}. - -...@item -fdump-rtl-sms -...@opindex fdump-rtl-sms -Dump after modulo scheduling, to @fi...@var{file}.136r.sms}. +...@option{-fdump-rtl-loop2} enables dumping after the rtl +loop optimization passes. @item -fdump-rtl-mach @opindex fdump-rtl-mach -Dump after performing the machine dependent reorganization pass, to -...@file{@var{file}.155r.mach} if that pass exists. +Dump after performing the machine dependent reorganization pass, if that +pass exists. + +...@item -fdump-rtl-mode_sw +...@opindex fdump-rtl-mode_sw +Dump after removing redundant mode switches. @item -fdump-rtl-rnreg @opindex fdump-rtl-rnreg -Dump after register renumbering, to @fi...@var{file}.147r.rnreg}. +Dump after register renumbering. -...@item -fdump-rtl-regmove -...@opindex fdump-rtl-regmove -Dump after the register move pass, to @fi...@var{file}.132r.regmove}. +...@itemx -fdump-rtl-outof_cfglayout +...@opindex fdump-rtl-outof_cfglayout +Dump after converting from cfglayout mode. + +...@item -fdump-rtl-peephole2 +...@opindex fdump-rtl-peephole2 +Dump after the peephole pass. @item -fdump-rtl-postreload @opindex fdump-rtl-postreload -Dump after post-reload optimizations, to @fi...@var{file}.24.postreload}. +Dump after post-reload optimizations. -...@item -fdump-rtl-expand -...@opindex fdump-rtl-expand -Dump after RTL generation, to @fi...@var{file}.104r.expand}. +...@itemx -fdump-rtl-pro_and_epilogue +...@opindex fdump-rtl-pro_and_epilogue +Dump after generating the function pro and epilogues. -...@item -fdump-rtl-sched2 -...@opindex fdump-rtl-sched2 -Dump after the second scheduling pass, to @fi...@var{file}.149r.sched2}. - -...@item -fdump-rtl-cse -...@opindex fdump-rtl-cse -Dump after CSE (including the jump optimization that sometimes follows -CSE), to @fi...@var{file}.113r.cse}. +...@item -fdump-rtl-regmove +...@opindex fdump-rtl-regmove +Dump after the register move pass. @item -fdump-rtl-sched1 +...@itemx -fdump-rtl-sched2 @opindex fdump-rtl-sched1 -Dump after the first scheduling pass, to @fi...@var{file}.136r.sched1}. +...@opindex fdump-rtl-sched2 +...@option{-fdump-rtl-sched1} and @option{-fdump-rtl-sched2} enable dumping +after the basic block scheduling passes. -...@item -fdump-rtl-cse2 -...@opindex fdump-rtl-cse2 -Dump after the second CSE pass (including the jump optimization that -sometimes follows CSE), to @fi...@var{file}.127r.cse2}. +...@item -fdump-rtl-see +...@opindex fdump-rtl-see +Dump after sign extension elimination. + +...@item -fdump-rtl-seqabstr +...@opindex fdump-rtl-seqabstr +Dump after common sequence discovery. + +...@item -fdump-rtl-shorten +...@opindex fdump-rtl-shorten +Dump after shortening branches. + +...@item -fdump-rtl-sibling +...@opindex fdump-rtl-sibling +Dump after sibling call optimizations. + +...@item -fdump-rtl-split1 +...@itemx -fdump-rtl-split2 +...@itemx -fdump-rtl-split3 +...@itemx -fdump-rtl-split4 +...@itemx -fdump-rtl-split5 +...@opindex fdump-rtl-split1 +...@opindex fdump-rtl-split2 +...@opindex fdump-rtl-split3 +...@opindex fdump-rtl-split4 +...@opindex fdump-rtl-split5 +...@option{-fdump-rtl-split1}, @option{-fdump-rtl-split2}, +...@option{-fdump-rtl-split3}, @option{-fdump-rtl-split4} and +...@option{-fdump-rtl-split5} enable dumping after five rounds of +instruction splitting. + +...@item -fdump-rtl-sms +...@opindex fdump-rtl-sms +Dump after modulo scheduling. This pass is only run on some +architectures. -...@item -fdump-rtl-tracer -...@opindex fdump-rtl-tracer -Dump after running tracer, to @fi...@var{file}.118r.tracer}. - -...@item -fdump-rtl-vpt -...@itemx -fdump-rtl-vartrack -...@opindex fdump-rtl-vpt +...@item -fdump-rtl-stack +...@opindex fdump-rtl-stack +Dump after conversion from GCC's "flat register file" registers to the +x87's stack-like registers. This pass is only run on x86 variants. + +...@item -fdump-rtl-subreg1 +...@itemx -fdump-rtl-subreg2 +...@opindex fdump-rtl-subreg1 +...@opindex fdump-rtl-subreg2 +...@option{-fdump-rtl-subreg1} and @option{-fdump-rtl-subreg2} enable dumping after +the two subreg expansion passes. + +...@item -fdump-rtl-unshare +...@opindex fdump-rtl-unshare +Dump after all rtl has been unshared. + +...@item -fdump-rtl-vartrack @opindex fdump-rtl-vartrack -...@option{-fdump-rtl-vpt} enable dumping after the value -profile transformations, to @fi...@var{file}.10.vpt}. -...@option{-fdump-rtl-vartrack} enable dumping after variable tracking, -to @fi...@var{file}.154r.vartrack}. - -...@item -fdump-rtl-flow2 -...@opindex fdump-rtl-flow2 -Dump after the second flow pass, to @fi...@var{file}.142r.flow2}. +Dump after variable tracking. -...@item -fdump-rtl-peephole2 -...@opindex fdump-rtl-peephole2 -Dump after the peephole pass, to @fi...@var{file}.145r.peephole2}. +...@item -fdump-rtl-vregs +...@opindex fdump-rtl-vregs +Dump after converting virtual registers to hard registers. @item -fdump-rtl-web @opindex fdump-rtl-web -Dump after live range splitting, to @fi...@var{file}.126r.web}. +Dump after live range splitting. + +...@item -fdump-rtl-regclass +...@itemx -fdump-rtl-subregs_of_mode_init +...@itemx -fdump-rtl-subregs_of_mode_finish +...@itemx -fdump-rtl-dfinit +...@itemx -fdump-rtl-dfinish +...@opindex fdump-rtl-regclass +...@opindex fdump-rtl-subregs_of_mode_init +...@opindex fdump-rtl-subregs_of_mode_finish +...@opindex fdump-rtl-dfinit +...@opindex fdump-rtl-dfinish +These dumps are defined but always produce empty files. @item -fdump-rtl-all @opindex fdump-rtl-all Produce all the dumps listed above. +...@item -dA +...@opindex dA +Annotate the assembler output with miscellaneous debugging information. + +...@item -dD +...@opindex dD +Dump all macro definitions, at the end of preprocessing, in addition to +normal output. + @item -dH @opindex dH Produce a core dump whenever an error occurs. Index: auto-inc-dec.c =================================================================== --- auto-inc-dec.c (revision 143754) +++ auto-inc-dec.c (working copy) @@ -1544,7 +1544,7 @@ struct rtl_opt_pass pass_inc_dec = { { RTL_PASS, - "auto-inc-dec", /* name */ + "auto_inc_dec", /* name */ gate_auto_inc_dec, /* gate */ rest_of_handle_auto_inc_dec, /* execute */ NULL, /* sub */ Index: mode-switching.c =================================================================== --- mode-switching.c (revision 143754) +++ mode-switching.c (working copy) @@ -760,7 +760,7 @@ struct rtl_opt_pass pass_mode_switching { { RTL_PASS, - "mode-sw", /* name */ + "mode_sw", /* name */ gate_mode_switching, /* gate */ rest_of_handle_mode_switching, /* execute */ NULL, /* sub */ Index: except.c =================================================================== --- except.c (revision 143754) +++ except.c (working copy) @@ -3332,7 +3332,7 @@ struct rtl_opt_pass pass_convert_to_eh_r { { RTL_PASS, - "eh-ranges", /* name */ + "eh_ranges", /* name */ NULL, /* gate */ convert_to_eh_region_ranges, /* execute */ NULL, /* sub */ Index: lower-subreg.c =================================================================== --- lower-subreg.c (revision 143754) +++ lower-subreg.c (working copy) @@ -1325,7 +1325,7 @@ struct rtl_opt_pass pass_lower_subreg = { { RTL_PASS, - "subreg", /* name */ + "subreg1", /* name */ gate_handle_lower_subreg, /* gate */ rest_of_handle_lower_subreg, /* execute */ NULL, /* sub */ Index: testsuite/gcc.dg/lower-subreg-1.c =================================================================== --- testsuite/gcc.dg/lower-subreg-1.c (revision 143754) +++ testsuite/gcc.dg/lower-subreg-1.c (working copy) @@ -1,8 +1,8 @@ /* { dg-do compile { target { { { ! mips64 } && { ! ia64-*-* } } && { ! spu-*-* } } } } */ -/* { dg-options "-O -fdump-rtl-subreg" } */ +/* { dg-options "-O -fdump-rtl-subreg1" } */ /* { dg-require-effective-target ilp32 } */ long long test (long long a, long long b) { return a | b; } -/* { dg-final { scan-rtl-dump "Splitting reg" "subreg" } } */ -/* { dg-final { cleanup-rtl-dump "subreg" } } */ +/* { dg-final { scan-rtl-dump "Splitting reg" "subreg1" } } */ +/* { dg-final { cleanup-rtl-dump "subreg1" } } */ -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35854