https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87485
--- Comment #18 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
(In reply to Vladimir Makarov from comment #17)
> I've reproduced it. Clearly, it is some bug in LRA conflict calculation.
> I will be working on it.
I investigated it more. Before scheduling we have
(insn 60 122 61 7 (parallel [
(set (subreg:DI (reg:TI 125) 0)
(zero_extend:DI (udiv:SI (reg:SI 116)
(reg:SI 119))))
(set (reg:SI 118)
(umod:SI (reg:SI 116)
(reg:SI 119)))
(clobber (reg:CC 17 flags))
...
(insn 90 69 92 7 (set (reg/i:SI 0 ax)
(const_int 0 [0])) "pr87485.c":34:1 67 {*movsi_internal}
(nil))
After scheduling we have
(insn 90 54 60 7 (set (reg/i:SI 0 ax)
(const_int 0 [0])) "pr87485.c":34:1 67 {*movsi_internal}
(nil))
(insn 60 90 61 7 (parallel [
(set (subreg:DI (reg:TI 125) 0)
(zero_extend:DI (udiv:SI (reg:SI 116)
(reg:SI 119))))
(set (reg:SI 118)
(umod:SI (reg:SI 116)
(reg:SI 119)))
(clobber (reg:CC 17 flags))
No way, RA can allocate ax for insn 60. So it is typical problem for 1st
insn scheduling on x86/x86-64. That is why it is switched off by default on
this target.
-fsched-presure and hard reg splitting in lra does not work for this case.
Unfortunately, they are not panacea.
I'll look what can I do in hard register splitting but I am bit pessimistic
that it will be fixed soon.
