https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114575
Bug ID: 114575
Summary: [14 Regression] SVE addressing modes broken since
g:839bc42772ba7af66af3bd16efed4a69511312ae
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Keywords: missed-optimization
Severity: normal
Priority: P3
Component: rtl-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: tnfchris at gcc dot gnu.org
Target Milestone: ---
Target: aarch64*
Created attachment 57864
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=57864&action=edit
addr.cc
Since the offending commit, compiling the example attached with -O3
-march=armv8.5-a+sve2 results in:
.L14:
lsl x0, x1, 1
add x1, x1, 8
add x2, x3, x0
add x6, x0, x4
ld1h z2.h, p7/z, [x2]
ld1h z22.h, p7/z, [x6]
add x0, x0, x5
fmad z22.h, p7/m, z21.h, z2.h
ld1h z20.h, p7/z, [x0]
fmad z20.h, p7/m, z26.h, z22.h
st1h z20.h, p7, [x2]
cmp x1, 808
bne .L14
instead of what it was before the commit:
.L14:
ld1h z2.h, p7/z, [x1, x0, lsl 1]
ld1h z22.h, p7/z, [x2, x0, lsl 1]
ld1h z20.h, p7/z, [x3, x0, lsl 1]
fmad z22.h, p7/m, z21.h, z2.h
fmad z20.h, p7/m, z26.h, z22.h
st1h z20.h, p7, [x1, x0, lsl 1]
add x0, x0, 8
cmp x0, 808
bne .L14
It's now no longer pushing in the register shifts. This causes significant
performance loss as it needs to now perform the integer ALU ops before doing
the load and they're on the critical path.
