Ping
On Sat, Dec 18, 2010 at 3:30 AM, Carrot Wei <car...@google.com> wrote:
> On Fri, Dec 17, 2010 at 4:18 AM, Richard Earnshaw <rearn...@arm.com> wrote:
>>
>> On Thu, 2010-12-16 at 14:45 -0800, Carrot Wei wrote:
>>> Hi
>>>
>>> Compile the following c code with options -march=armv7-a -mthumb -Os
>>>
>>> int foo (int s)
>>> {
>>> return s == 1;
>>> }
>>>
>>> GCC 4.6 generates:
>>>
>>> 00000000 <foo>:
>>> 0: f1a0 0301 sub.w r3, r0, #1 // A
>>> 4: 4258 negs r0, r3
>>> 6: eb40 0003 adc.w r0, r0, r3 // B
>>> a: 4770 bx lr
>>>
>>> Notice that instructions A and B are 32 bits. In thumb2 we can use subs and
>>> adcs
>>> instead so they will be 16 bits.
>>>
>>
>> This sequence already contains an instruction that sets the flags as a
>> necessary part of the sequence. Why doesn't it also generate
>> flag-corrupting variants of the other two instructions when the
>
> That is the root cause of this problem. The old pattern simply didn't
> generate the flag setting version.
>
>> registers selected are suitable? It seems silly to force the compiler
>> to do yet more work to clean up this code.
>>
>
> This patch doesn't force the compiler to do more work. It directly
> modifies the original peephole2 pattern to generate flag setting
> instructions as you suggested. And the new insn pattern is for
> instruction adcs which didn't exist previously.
>
> thanks
> Guozhi
>
