Some higher priority FMV features were dependent subsets of lower priority features. Fix this, using the new priorities specified in https://github.com/ARM-software/acle/pull/279.
gcc/ChangeLog: * config/aarch64/aarch64-option-extensions.def: Reorder FMV entries. gcc/testsuite/ChangeLog: * gcc.target/aarch64/cpunative/native_cpu_21.c: Reorder features. * gcc.target/aarch64/cpunative/native_cpu_22.c: Ditto. diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index aa3cd99f791c83c5b15291503f3375a7cf2732cd..0078dd092884a94d2a339b5238b8d19747ff9fa1 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -99,17 +99,17 @@ AARCH64_OPT_EXTENSION(NAME, IDENT, REQUIRES, EXPLICIT_ON, EXPLICIT_OFF, \ AARCH64_FMV_FEATURE(NAME, IDENT, (IDENT)) -AARCH64_OPT_EXTENSION("fp", FP, (), (), (), "fp") - -AARCH64_OPT_EXTENSION("simd", SIMD, (FP), (), (), "asimd") - AARCH64_OPT_FMV_EXTENSION("rng", RNG, (), (), (), "rng") AARCH64_OPT_FMV_EXTENSION("flagm", FLAGM, (), (), (), "flagm") AARCH64_FMV_FEATURE("flagm2", FLAGM2, (FLAGM)) -AARCH64_FMV_FEATURE("fp16fml", FP16FML, (F16FML)) +AARCH64_OPT_FMV_EXTENSION("lse", LSE, (), (), (), "atomics") + +AARCH64_OPT_FMV_EXTENSION("fp", FP, (), (), (), "fp") + +AARCH64_OPT_FMV_EXTENSION("simd", SIMD, (FP), (), (), "asimd") AARCH64_OPT_FMV_EXTENSION("dotprod", DOTPROD, (SIMD), (), (), "asimddp") @@ -121,12 +121,6 @@ AARCH64_OPT_EXTENSION("rdma", RDMA, (), (SIMD), (), "asimdrdm") AARCH64_FMV_FEATURE("rmd", RDM, (RDMA)) -AARCH64_OPT_FMV_EXTENSION("lse", LSE, (), (), (), "atomics") - -AARCH64_FMV_FEATURE("fp", FP, (FP)) - -AARCH64_FMV_FEATURE("simd", SIMD, (SIMD)) - AARCH64_OPT_FMV_EXTENSION("crc", CRC, (), (), (), "crc32") AARCH64_FMV_FEATURE("sha1", SHA1, ()) @@ -160,6 +154,8 @@ AARCH64_FMV_FEATURE("fp16", FP16, (F16)) -march=armv8.4-a+nofp16+fp16 enables F16 but not F16FML. */ AARCH64_OPT_EXTENSION("fp16fml", F16FML, (), (F16), (), "asimdfhm") +AARCH64_FMV_FEATURE("fp16fml", FP16FML, (F16FML)) + AARCH64_FMV_FEATURE("dit", DIT, ()) AARCH64_FMV_FEATURE("dpb", DPB, ()) diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c index 920e1d65711cbcb77b07441597180c0159ccabf9..1d90e9ec9d971ae0f085fd832099058488c817b8 100644 --- a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c @@ -7,7 +7,7 @@ int main() return 0; } -/* { dg-final { scan-assembler {\.arch armv8-a\+flagm\+dotprod\+rdma\+lse\+crc\+fp16fml\+rcpc\+i8mm\+bf16\+sve2-aes\+sve2-bitperm\+sve2-sha3\+sve2-sm4\+sb\+ssbs\n} } } */ +/* { dg-final { scan-assembler {\.arch armv8-a\+flagm\+lse\+dotprod\+rdma\+crc\+fp16fml\+rcpc\+i8mm\+bf16\+sve2-aes\+sve2-bitperm\+sve2-sha3\+sve2-sm4\+sb\+ssbs\n} } } */ /* Check that an Armv8-A core doesn't fall apart on extensions without midr values. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c index 416a29b514ab7599a7092e26e3716ec8a50cc895..17050a0b72c98ecfd87ec5f7f522cce4db9efc16 100644 --- a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c @@ -7,7 +7,7 @@ int main() return 0; } -/* { dg-final { scan-assembler {\.arch armv8-a\+flagm\+dotprod\+rdma\+lse\+crc\+fp16fml\+rcpc\+i8mm\+bf16\+sve2-aes\+sve2-bitperm\+sve2-sha3\+sve2-sm4\+sb\+ssbs\+pauth\n} } } */ +/* { dg-final { scan-assembler {\.arch armv8-a\+flagm\+lse\+dotprod\+rdma\+crc\+fp16fml\+rcpc\+i8mm\+bf16\+sve2-aes\+sve2-bitperm\+sve2-sha3\+sve2-sm4\+sb\+ssbs\+pauth\n} } } */ /* Check that an Armv8-A core doesn't fall apart on extensions without midr values and that it enables optional features. */