Thanks Edwin, should be one silly mistake, will fix it ASAP. Pan
-----Original Message----- From: Edwin Lu <e...@rivosinc.com> Sent: Friday, April 12, 2024 5:20 AM To: Li, Pan2 <pan2...@intel.com>; Bernd Edlinger <bernd.edlin...@hotmail.de>; Kito Cheng <kito.ch...@gmail.com>; juzhe.zh...@rivai.ai Cc: gcc-patches <gcc-patches@gcc.gnu.org> Subject: Re: [PATCH v1] RISC-V: Bugfix ICE for the vector return arg in mode switch On 4/11/2024 5:45 AM, Li, Pan2 wrote: > Thanks for reporting this. Just take a look from my test log that 930623-1.c > is all pass. > > Thus I bet this difference comes from the build option --with-arch=rv32imac > but my test script take rv64gcv. > >> I've built the git revision f3fdcf4a37a with >> ../gcc-trunk/configure --target=riscv-unknown-elf >> --prefix=/home/ed/gnu/riscv-unknown-elf --enable-languages=c,c++ >> --disable-multilib --with-arch=rv32imac --with-abi=ilp32 > >> I am a bit surprised since the target is not supposed to support floating >> point >> or vector instructions AFAIK. > > Because you specify rv32imac, with doesn't include f/d/v extension, aka > single/double floating point and vector extension. Thus, related > functionality are disabled. > >> The issue does not happen with gcc-trunk from yesterday. > > Ack, will look into it. > > Pan > Hi Pan, Our postcommit-ci found that it breaks for non-vector targets on rv32/64 newlib/linux https://github.com/patrick-rivos/gcc-postcommit-ci/issues/757. The patchwork precommit-ci also appeared to have flagged it https://github.com/ewlu/gcc-precommit-ci/issues/1417#issuecomment-2048846532 Edwin
