Hi
I updated this patch to use const_ok_for_dimode_op to decide if a
const is legal for iordi3 insn. The special cases of all 0 and all 1
constant are also handled.
Tested on arm qemu with all thumb/arm neon/non-neon combination, no regression.
thanks
Carrot
2012-07-06 Wei Guozhi <car...@google.com>
PR target/53189
* gcc.target/arm/pr53189-7.c: New testcase.
* gcc.target/arm/pr53189-8.c: New testcase.
* gcc.target/arm/pr53189-9.c: New testcase.
2012-07-06 Wei Guozhi <car...@google.com>
PR target/53189
* config/arm/arm.c (const_ok_for_dimode_op): Handle IOR op.
* config/arm/constraints.md (Df): New constraint.
* config/arm/predicates.md (arm_iordi_operand): New predicate.
(arm_immediate_iordi_operand): Likewise.
(iordi_operand): Likewise.
* config/arm/arm.md (iorsi3_insn): Optimization for special constants.
(iordi3): Extend it to handle 64bit constants.
(iordi3_insn): Likewise.
* config/arm/neon.md (iordi3_neon): Likewise.
Index: gcc/testsuite/gcc.target/arm/pr53189-7.c
===================================================================
--- gcc/testsuite/gcc.target/arm/pr53189-7.c (revision 0)
+++ gcc/testsuite/gcc.target/arm/pr53189-7.c (revision 0)
@@ -0,0 +1,8 @@
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-final { scan-assembler-not "mov" } } */
+
+void t0p(long long * p)
+{
+ *p |= 0x100000008;
+}
Index: gcc/testsuite/gcc.target/arm/pr53189-8.c
===================================================================
--- gcc/testsuite/gcc.target/arm/pr53189-8.c (revision 0)
+++ gcc/testsuite/gcc.target/arm/pr53189-8.c (revision 0)
@@ -0,0 +1,9 @@
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-final { scan-assembler-times "mvn" 1 } } */
+/* { dg-final { scan-assembler-times "orr" 1 } } */
+
+void t0p(long long * p)
+{
+ *p |= 0x1FFFFFFFF;
+}
Index: gcc/testsuite/gcc.target/arm/pr53189-9.c
===================================================================
--- gcc/testsuite/gcc.target/arm/pr53189-9.c (revision 0)
+++ gcc/testsuite/gcc.target/arm/pr53189-9.c (revision 0)
@@ -0,0 +1,9 @@
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-final { scan-assembler-not "mov" } } */
+/* { dg-final { scan-assembler-times "orr" 1 } } */
+
+void t0p(long long * p)
+{
+ *p |= 0x100000000;
+}
Index: gcc/config/arm/arm.c
===================================================================
--- gcc/config/arm/arm.c (revision 189278)
+++ gcc/config/arm/arm.c (working copy)
@@ -2524,6 +2524,16 @@
case PLUS:
return arm_not_operand (hi, SImode) && arm_add_operand (lo, SImode);
+ case IOR:
+ if ((const_ok_for_arm (hi_val) || (hi_val == 0xFFFFFFFF))
+ && (const_ok_for_arm (lo_val) || (lo_val == 0xFFFFFFFF)))
+ return 1;
+ if (TARGET_THUMB2
+ && (const_ok_for_arm (lo_val) || const_ok_for_arm (~lo_val))
+ && (const_ok_for_arm (hi_val) || const_ok_for_arm (~hi_val)))
+ return 1;
+ return 0;
+
default:
return 0;
}
Index: gcc/config/arm/neon.md
===================================================================
--- gcc/config/arm/neon.md (revision 189278)
+++ gcc/config/arm/neon.md (working copy)
@@ -731,9 +731,9 @@
)
(define_insn "iordi3_neon"
- [(set (match_operand:DI 0 "s_register_operand" "=w,w,?&r,?&r,?w,?w")
- (ior:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,r,w,0")
- (match_operand:DI 2 "neon_logic_op2" "w,Dl,r,r,w,Dl")))]
+ [(set (match_operand:DI 0 "s_register_operand" "=w,w,?&r,?&r,?w,?w,?&r,?&r")
+ (ior:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,r,w,0,0,r")
+ (match_operand:DI 2 "iordi_operand" "w,Dl,r,r,w,Dl,Df,Df")))]
"TARGET_NEON"
{
switch (which_alternative)
@@ -745,12 +745,14 @@
DImode, 0, VALID_NEON_QREG_MODE (DImode));
case 2: return "#";
case 3: return "#";
+ case 6: return "#";
+ case 7: return "#";
default: gcc_unreachable ();
}
}
- [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*,neon_int_1,neon_int_1")
- (set_attr "length" "*,*,8,8,*,*")
- (set_attr "arch" "nota8,nota8,*,*,onlya8,onlya8")]
+ [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*,neon_int_1,neon_int_1,*,*")
+ (set_attr "length" "*,*,8,8,*,*,8,8")
+ (set_attr "arch" "nota8,nota8,*,*,onlya8,onlya8,*,*")]
)
;; The concrete forms of the Neon immediate-logic instructions are vbic and
Index: gcc/config/arm/constraints.md
===================================================================
--- gcc/config/arm/constraints.md (revision 189278)
+++ gcc/config/arm/constraints.md (working copy)
@@ -31,7 +31,7 @@
;; 'H' was previously used for FPA.
;; The following multi-letter normal constraints have been used:
-;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, Dl, DL, Dv, Dy, Di, Dt, Dz
+;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Df, Dn, Dl, DL, Dv, Dy, Di, Dt, Dz
;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py
@@ -248,6 +248,12 @@
(and (match_code "const_int")
(match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, PLUS)")))
+(define_constraint "Df"
+ "@internal
+ In ARM/Thumb-2 state a const_int that can be used by iordi3_insn."
+ (and (match_code "const_int")
+ (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, IOR)")))
+
(define_constraint "Di"
"@internal
In ARM/Thumb-2 state a const_int or const_double where both the high
Index: gcc/config/arm/predicates.md
===================================================================
--- gcc/config/arm/predicates.md (revision 189278)
+++ gcc/config/arm/predicates.md (working copy)
@@ -104,6 +104,14 @@
(and (match_code "const_int,const_double")
(match_test "arm_const_double_by_immediates (op)")))
+(define_predicate "arm_immediate_iordi_operand"
+ (and (match_code "const_int")
+ (match_test "const_ok_for_dimode_op (INTVAL (op), IOR)")))
+
+(define_predicate "arm_iordi_operand"
+ (ior (match_operand 0 "arm_immediate_iordi_operand")
+ (match_operand 0 "s_register_operand")))
+
(define_predicate "arm_neg_immediate_operand"
(and (match_code "const_int")
(match_test "const_ok_for_arm (-INTVAL (op))")))
@@ -520,6 +528,10 @@
(ior (match_operand 0 "imm_for_neon_logic_operand")
(match_operand 0 "s_register_operand")))
+(define_predicate "iordi_operand"
+ (ior (match_operand 0 "neon_logic_op2")
+ (match_operand 0 "arm_iordi_operand")))
+
(define_predicate "neon_inv_logic_op2"
(ior (match_operand 0 "imm_for_neon_inv_logic_operand")
(match_operand 0 "s_register_operand")))
Index: gcc/config/arm/arm.md
===================================================================
--- gcc/config/arm/arm.md (revision 189278)
+++ gcc/config/arm/arm.md (working copy)
@@ -2828,17 +2828,30 @@
(define_expand "iordi3"
[(set (match_operand:DI 0 "s_register_operand" "")
(ior:DI (match_operand:DI 1 "s_register_operand" "")
- (match_operand:DI 2 "neon_logic_op2" "")))]
+ (match_operand:DI 2 "iordi_operand" "")))]
"TARGET_32BIT"
""
)
-(define_insn "*iordi3_insn"
- [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
- (ior:DI (match_operand:DI 1 "s_register_operand" "%0,r")
- (match_operand:DI 2 "s_register_operand" "r,r")))]
+(define_insn_and_split "*iordi3_insn"
+ [(set (match_operand:DI 0 "s_register_operand" "=&r,&r,&r,&r")
+ (ior:DI (match_operand:DI 1 "s_register_operand" "%0,r, 0, r")
+ (match_operand:DI 2 "arm_iordi_operand" "r, r, Df,Df")))]
"TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON"
"#"
+ "TARGET_32BIT && !TARGET_IWMMXT && reload_completed
+ && !(TARGET_NEON && IS_VFP_REGNUM (REGNO (operands[0])))"
+ [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 2)))
+ (set (match_dup 3) (ior:SI (match_dup 4) (match_dup 5)))]
+ "
+ {
+ operands[3] = gen_highpart (SImode, operands[0]);
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ operands[4] = gen_highpart (SImode, operands[1]);
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ operands[5] = gen_highpart_mode (SImode, DImode, operands[2]);
+ operands[2] = gen_lowpart (SImode, operands[2]);
+ }"
[(set_attr "length" "8")
(set_attr "predicable" "yes")]
)
@@ -2902,10 +2915,29 @@
(ior:SI (match_operand:SI 1 "s_register_operand" "%r,r,r")
(match_operand:SI 2 "reg_or_int_operand" "rI,K,?n")))]
"TARGET_32BIT"
- "@
- orr%?\\t%0, %1, %2
- orn%?\\t%0, %1, #%B2
- #"
+ "*
+ {
+ if (CONST_INT_P (operands[2]))
+ {
+ HOST_WIDE_INT i = INTVAL (operands[2]) & 0xFFFFFFFF;
+ if (i == 0xFFFFFFFF)
+ return \"mvn%?\\t%0, #0\";
+ if (i == 0)
+ {
+ if (!rtx_equal_p (operands[0], operands[1]))
+ return \"mov%?\\t%0, %1\";
+ else
+ return \"\";
+ }
+ }
+
+ switch (which_alternative)
+ {
+ case 0: return \"orr%?\\t%0, %1, %2\";
+ case 1: return \"orn%?\\t%0, %1, #%B2\";
+ case 2: return \"#\";
+ }
+ }"
"TARGET_32BIT
&& GET_CODE (operands[2]) == CONST_INT
&& !(const_ok_for_arm (INTVAL (operands[2]))
On Tue, Jun 5, 2012 at 5:14 PM, Carrot Wei <car...@google.com> wrote:
> Hi
>
> This is the fourth part of the patches that deals with 64bit ior. It directly
> extends the patterns iordi3, iordi3_insn and iordi3_neon to handle 64bit
> constant operands.
>
> Tested on arm qemu without regression.
>
> OK for trunk?
>
> thanks
> Carrot
>
> 2012-06-05 Wei Guozhi <car...@google.com>
>
> PR target/53447
> * gcc.target/arm/pr53447-4.c: New testcase.
>
>
> 2012-06-05 Wei Guozhi <car...@google.com>
>
> PR target/53447
> * config/arm/arm-protos.h (const_ok_for_iordi): New prototype.
> * config/arm/arm.c (const_ok_for_iordi): New function.
> * config/arm/constraints.md (Df): New constraint.
> * config/arm/predicates.md (arm_iordi_operand): New predicate.
> (arm_immediate_iordi_operand): Likewise.
> (iordi_operand): Likewise.
> * config/arm/arm.md (iordi3): Extend it to handle 64bit constants.
> (iordi3_insn): Likewise.
> * config/arm/neon.md (iordi3_neon): Likewise.
>
>
> Index: testsuite/gcc.target/arm/pr53447-4.c
> ===================================================================
> --- testsuite/gcc.target/arm/pr53447-4.c (revision 0)
> +++ testsuite/gcc.target/arm/pr53447-4.c (revision 0)
> @@ -0,0 +1,8 @@
> +/* { dg-options "-O2" } */
> +/* { dg-require-effective-target arm32 } */
> +/* { dg-final { scan-assembler-not "mov" } } */
> +
> +void t0p(long long * p)
> +{
> + *p |= 0x100000008;
> +}
>
>
> Index: config/arm/arm.c
> ===================================================================
> --- config/arm/arm.c (revision 188048)
> +++ config/arm/arm.c (working copy)
> @@ -2496,6 +2496,24 @@
> }
> }
>
> +/* Return TRUE if int I is a valid immediate constant used by pattern
> + iordi3_insn. */
> +int
> +const_ok_for_iordi (HOST_WIDE_INT i)
> +{
> + HOST_WIDE_INT high = ARM_SIGN_EXTEND ((i >> 32) & 0xFFFFFFFF);
> + HOST_WIDE_INT low = ARM_SIGN_EXTEND (i & 0xFFFFFFFF);
> +
> + if (TARGET_32BIT && const_ok_for_arm (low) && const_ok_for_arm (high))
> + return 1;
> +
> + if (TARGET_THUMB2 && (const_ok_for_arm (low) || const_ok_for_arm (~low))
> + && (const_ok_for_arm (high) || const_ok_for_arm (~high)))
> + return 1;
> +
> + return 0;
> +}
> +
> /* Emit a sequence of insns to handle a large constant.
> CODE is the code of the operation required, it can be any of SET, PLUS,
> IOR, AND, XOR, MINUS;
> Index: config/arm/arm-protos.h
> ===================================================================
> --- config/arm/arm-protos.h (revision 188048)
> +++ config/arm/arm-protos.h (working copy)
> @@ -47,6 +47,7 @@
> extern bool arm_small_register_classes_for_mode_p (enum machine_mode);
> extern int arm_hard_regno_mode_ok (unsigned int, enum machine_mode);
> extern bool arm_modes_tieable_p (enum machine_mode, enum machine_mode);
> +extern int const_ok_for_iordi (HOST_WIDE_INT);
> extern int const_ok_for_arm (HOST_WIDE_INT);
> extern int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
> extern int arm_split_constant (RTX_CODE, enum machine_mode, rtx,
> Index: config/arm/neon.md
> ===================================================================
> --- config/arm/neon.md (revision 188048)
> +++ config/arm/neon.md (working copy)
> @@ -729,9 +729,9 @@
> )
>
> (define_insn "iordi3_neon"
> - [(set (match_operand:DI 0 "s_register_operand" "=w,w,?&r,?&r,?w,?w")
> - (ior:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,r,w,0")
> - (match_operand:DI 2 "neon_logic_op2" "w,Dl,r,r,w,Dl")))]
> + [(set (match_operand:DI 0 "s_register_operand"
> "=w,w,?&r,?&r,?w,?w,?&r,?&r")
> + (ior:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,r,w,0,0,r")
> + (match_operand:DI 2 "iordi_operand" "w,Dl,r,r,w,Dl,Df,Df")))]
> "TARGET_NEON"
> {
> switch (which_alternative)
> @@ -743,12 +743,14 @@
> DImode, 0, VALID_NEON_QREG_MODE (DImode));
> case 2: return "#";
> case 3: return "#";
> + case 6: return "#";
> + case 7: return "#";
> default: gcc_unreachable ();
> }
> }
> - [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*,neon_int_1,neon_int_1")
> - (set_attr "length" "*,*,8,8,*,*")
> - (set_attr "arch" "nota8,nota8,*,*,onlya8,onlya8")]
> + [(set_attr "neon_type"
> "neon_int_1,neon_int_1,*,*,neon_int_1,neon_int_1,*,*")
> + (set_attr "length" "*,*,8,8,*,*,8,8")
> + (set_attr "arch" "nota8,nota8,*,*,onlya8,onlya8,*,*")]
> )
>
> ;; The concrete forms of the Neon immediate-logic instructions are vbic and
> Index: config/arm/constraints.md
> ===================================================================
> --- config/arm/constraints.md (revision 188048)
> +++ config/arm/constraints.md (working copy)
> @@ -29,7 +29,7 @@
> ;; in Thumb-1 state: I, J, K, L, M, N, O
>
> ;; The following multi-letter normal constraints have been used:
> -;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dt, Dz
> +;; in ARM/Thumb-2 state: Da, Db, Dc, Df, Dn, Dl, DL, Dv, Dy, Di, Dt, Dz
> ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
> ;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py
>
> @@ -251,6 +251,12 @@
> (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
> && !(optimize_size || arm_ld_sched)")))
>
> +(define_constraint "Df"
> + "@internal
> + In ARM/Thumb-2 state a const_int that can be used by iordi3_insn. "
> + (and (match_code "const_int")
> + (match_test "TARGET_32BIT && const_ok_for_iordi (ival)")))
> +
> (define_constraint "Di"
> "@internal
> In ARM/Thumb-2 state a const_int or const_double where both the high
> Index: config/arm/predicates.md
> ===================================================================
> --- config/arm/predicates.md (revision 188048)
> +++ config/arm/predicates.md (working copy)
> @@ -117,6 +117,14 @@
> (and (match_code "const_int,const_double")
> (match_test "arm_const_double_by_immediates (op)")))
>
> +(define_predicate "arm_immediate_iordi_operand"
> + (and (match_code "const_int")
> + (match_test "const_ok_for_iordi (INTVAL (op))")))
> +
> +(define_predicate "arm_iordi_operand"
> + (ior (match_operand 0 "arm_immediate_iordi_operand")
> + (match_operand 0 "s_register_operand")))
> +
> (define_predicate "arm_neg_immediate_operand"
> (and (match_code "const_int")
> (match_test "const_ok_for_arm (-INTVAL (op))")))
> @@ -547,6 +555,10 @@
> (ior (match_operand 0 "imm_for_neon_logic_operand")
> (match_operand 0 "s_register_operand")))
>
> +(define_predicate "iordi_operand"
> + (ior (match_operand 0 "neon_logic_op2")
> + (match_operand 0 "arm_iordi_operand")))
> +
> (define_predicate "neon_inv_logic_op2"
> (ior (match_operand 0 "imm_for_neon_inv_logic_operand")
> (match_operand 0 "s_register_operand")))
> Index: config/arm/arm.md
> ===================================================================
> --- config/arm/arm.md (revision 188048)
> +++ config/arm/arm.md (working copy)
> @@ -2854,17 +2854,38 @@
> (define_expand "iordi3"
> [(set (match_operand:DI 0 "s_register_operand" "")
> (ior:DI (match_operand:DI 1 "s_register_operand" "")
> - (match_operand:DI 2 "neon_logic_op2" "")))]
> + (match_operand:DI 2 "iordi_operand" "")))]
> "TARGET_32BIT"
> ""
> )
>
> -(define_insn "*iordi3_insn"
> - [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
> - (ior:DI (match_operand:DI 1 "s_register_operand" "%0,r")
> - (match_operand:DI 2 "s_register_operand" "r,r")))]
> +(define_insn_and_split "*iordi3_insn"
> + [(set (match_operand:DI 0 "s_register_operand" "=&r,&r,&r,&r")
> + (ior:DI (match_operand:DI 1 "s_register_operand" "%0,r,0,r")
> + (match_operand:DI 2 "arm_iordi_operand" "r,r,Df,Df")))]
> "TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON"
> "#"
> + "TARGET_32BIT && !TARGET_IWMMXT && reload_completed"
> + [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 2)))
> + (set (match_dup 3) (ior:SI (match_dup 4) (match_dup 5)))]
> + "
> + {
> + operands[3] = gen_highpart (SImode, operands[0]);
> + operands[0] = gen_lowpart (SImode, operands[0]);
> + operands[4] = gen_highpart (SImode, operands[1]);
> + operands[1] = gen_lowpart (SImode, operands[1]);
> + if (GET_CODE (operands[2]) == CONST_INT)
> + {
> + HOST_WIDE_INT v = INTVAL (operands[2]);
> + operands[5] = GEN_INT (ARM_SIGN_EXTEND ((v >> 32) & 0xFFFFFFFF));
> + operands[2] = GEN_INT (ARM_SIGN_EXTEND (v & 0xFFFFFFFF));
> + }
> + else
> + {
> + operands[5] = gen_highpart (SImode, operands[2]);
> + operands[2] = gen_lowpart (SImode, operands[2]);
> + }
> + }"
> [(set_attr "length" "8")
> (set_attr "predicable" "yes")]
> )
